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参数资料
| 型号： | GE28F008B3BA70 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46 |
| 封装： | VFBGA-46 |
| 文件页数： | 44/70页 |
| 文件大小： | 1215K |
| 代理商： | GE28F008B3BA70 |
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
49
9.0
Power and Reset Specifications
9.1
Power-Up/Down Characteristics
To prevent any condition that may result in a spurious write or erase operation, Intel recommends
that you power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-down
together. Intel also recommends power-up VPP with or slightly after VCC. Conversely, VPP must
powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCCMin before
applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin.
Power supply transitions must only occur when RP# is low.
9.1.1
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices because the
system expects to read from the flash memory when it exits reset. If a CPU reset occurs without a
flash memory reset, proper CPU initialization will not occur because the flash memory may be
providing status information instead of array data. Intel recommends connecting RP# to the system
CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Because
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can occur only after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
9.1.2
VCC, VPP, and RP# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage), is read-array mode.
After any program or Block-Erase operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read-array mode through the Read Array command if access to
the flash-memory array is required.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GE28F008B3BA90 | 制造商:Intel 功能描述: |
| GE28F008B3TA90 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:3 Volt Advanced Boot Block Flash Memory |
| GE28F128J3A-110 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| GE28F128J3A-115 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| GE28F128J3A-120 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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