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参数资料
| 型号： | GS4576S09L-25 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封装： | UBGA-144 |
| 文件页数： | 18/64页 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
25/64
2011, GSI Technology
Read
Read data transfers are launched with a Read command, as shown below. Read Addresses must provided with the Read command.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at the
outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also edge-
aligned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid
data edge generated at the Q signals associated with QK0 (tQKQ0 is referenced to Q0–Q8). tQKQ1 is the skew between QK1 and
the last valid data edge generated at the Q signals associated with QK1 (tQKQ1 is referenced to Q9–Q17). tQKQx is derived at
each QKx clock edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair and any
output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (Q) will go High-Z. The QVLD signal
transitions Low on the beat of a Read burst. Note that if CK/CK violates the VID(DC) specification while a Read burst is occurring,
QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a continuous
flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See
the Read Data Valid Window section for illustration.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write.
Read Command
A
BA
CK
CS
WE
REF
ADDRESS
BANK ADDRESS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS4576S18GL-24I | 制造商:GSI Technology 功能描述:32MB X 18 SEPARATE I/O - Trays |
| GS4576S18L-24I | 制造商:GSI Technology 功能描述:32MB X 18 SEPARATE I/O - Trays |
| GS4-6 | 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL RING 4MM 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL, RING, 4MM 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL, RING, 4MM; Connector Type:Ring Tongue; Termination Method:Crimp; Stud/Tab Size:4mm; Wire Size AWG Min:12AWG; Wire Size AWG Max:10AWG; SVHC:No SVHC (19-Dec-2012); Cable Diameter Max:3.6mm; Stud Size:4mm; Wire Area Size;RoHS Compliant: Yes |
| GS4-6 BR TIN | 制造商:STIMPSON 功能描述: |
| GS4-6 BRASS | 制造商:STIMPSON 功能描述: |
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