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参数资料
| 型号： | GS8152Z18 |
| 厂商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水线式和流通型同步NBT静态RAM) |
| 中文描述： | 16Mb的流水线和流量，通过同步唑的SRAM（1,600位流水线式和流通型同步唑静态内存） |
| 文件页数： | 15/39页 |
| 文件大小： | 757K |
| 代理商： | GS8152Z18 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
15/39
2000, Giga Semiconductor, Inc.
Preliminary
GS8152Z18/36/72B-225/200/180/166/150/133
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
ByteSafe
Parity Functions
In x64/x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x64/
x32/x16 mode because there is no source for parity bits from the system. So, in x64/x32/x16 mode, the device generates parity and
stores it along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
CK
ZZ
tZZR
tZZH
tZZS
~
~
Sleep
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