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| 型号： | GT-64010A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(带PCI接口用于R4XXX/ R5000 系列 CPUs的系统控制器) |
| 中文描述： | 系统控制器的PCI R4XXX接口/ R5000系列处理器（带的PCI接口用于R4XXX / R5000系列处理器的系统控制器） |
| 文件页数： | 2/111页 |
| 文件大小： | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
10
R e v i s ion 1 . 1
Galileo
TechnologyTM
4.4
Parity Support
Memory or device parity generation and checking is supported with external logic. The external logic should generate
parity in write accesses to devices and memory and check parity in read accesses. When a parity error is detected by
the external logic it needs to drive the ParErr* pin of the GT-64010A. The GT-64010A has a programmable parity integ-
rity bit for each bank, which indicates if parity is supported.
In read accesses by the CPU from a 72-bit bank DRAM or device, the GT-64010A will assert SysCmd[4] to indicate to
the CPU if it needs to check parity for the current access. In this case the GT-64010A relies on the CPU parity checking
mechanism. In CPU read accesses from a 32-bit device or memory, the GT-64010A will not assert SysCmd[4] even if
the bank that was accessed has the parity integrity bit set. If a parity error is detected in this case (indicated by Par-
Err*), the GT-64010A will return the data with SysCmd[5] asserted and will cause a parity error interrupt.
In DMA read accesses, detection of a parity error from a bank with the parity integrity bit set, will cause an interrupt.
In the case of PCI read accesses, the GT-64010A will assert SErr* if the bank that data was read from has the parity
integrity bit set, and will assert a parity error interrupt. The GT-64010A will generate and check word (32- bits) parity on
data that is read from the PCI with compliance to the PCI requirements for every transaction. A parity error detection on
the PCI will cause the assertion of PErr*. For the connection of memory buses, refer to section 8.
4.5
Memory Control
The GT64010A system can be assembled in different configurations which are up to the user.
There are two main configurations: without data latches on the AD bus, meaning that the system is implemented with a
32-bit or narrower bus, and with latches on the AD bus, which allows for 64-bit bus accesses.
For details regarding the connection of memory, see section 8.
4.6
DRAM Controller
The DRAM controller supports page mode and EDO DRAM. The depth of the DRAM devices can vary for each bank
separately from 256K to 16M, and the width of each bank can be 32- or 64-bits. With these options, each DRAM bank
size can vary from 1 Mbyte to 128 Mbytes. Furthermore, 0.5K, 1K, 2K, and 4K refresh DRAMs can be used, as well as
asymmetric RAS, CAS addressing.
Some of the DRAM timing parameters are programmable to allow for different system timing optimizations. RAS-to-
CAS delay can be programmed to two or three cycles, and CAS can be LOW for one or two cycles.
DRAM performance in CPU read accesses is 7-2-2-2, which means 4 wait states to first data and one wait state for
each additional double word. DMA and PCI burst accesses can be one per clock for a maximum of 8 consecutive 32-bit
words.
Refresh can be programmed to different frequencies of occurrences by the refresh counter. For example, if the refresh
counter is programmed to 0x200, then at 50MHz a refresh sequence will occur every 10uS (20nS x 200). Staggered
and non-staggered refresh modes are supported. In staggered mode, the four banks of DRAM will be refreshed with
one cycle delay between each bank, while in non-staggered mode all four banks will be refreshed together.
4.7
Device Controller
This controller has programmable timing parameters for each device bank to accommodate different device types (e.g.
Flash, SRAM, ROM, I/O Controllers). The devices share the local AD bus with the DRAM, but unlike the DRAM, the
devices use the AD bus as a multiplexed address and data bus. In the address phase, the device controller puts on the
bus 22-bits of address, four general purpose Chip Select signals (CS[3:0]*), one Boot Chip Select (BootCS*), four DMA
Acknowledge signals (DMAAck[3:0]*), and an indication as to whether the access is a read or write (DevRW*).
A bus cycle starts by the assertion of ALE and ADS* for one cycle when a CS* signal and/or a DMAAck* signal are
active. The CS* and DMAAck* need to be externally latched and qualified with CSTiming*. The CSTiming* signal will
be valid for the programmable number of cycles of the specific CS* that is active.
There are eight byte write signals, four for the even bank (EWr[3:0]*) and four for the odd bank (OWr[3:0]*). The write
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