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| 型号： | GT-64010A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(带PCI接口用于R4XXX/ R5000 系列 CPUs的系统控制器) |
| 中文描述： | 系统控制器的PCI R4XXX接口/ R5000系列处理器（带的PCI接口用于R4XXX / R5000系列处理器的系统控制器） |
| 文件页数： | 8/111页 |
| 文件大小： | 671K |
| 代理商： | GT-64010A |
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GT-64010A System Controller with PCI Interface for R4XXX/R5000 Family CPUs
105
Rev is io n 1. 1
Galileo
TechnologyTM
13.Appendices
13.1 GT-64010A Behavior With Little/big Endian Data Formats
13.1.1. Background
There are two bits in the GT-64010A which control byte swapping. One is located in the CPU Interface unit’s mode reg-
ister (0x000) bit 12, the other in PCI Interface unit’s command register (0xc00) bit 0. Both bits are given the same value
as sampled at reset via pullup/pulldown on Interrupt* pin. Both can be otherwise programmed after reset is deasserted.
As a master rule, if both bits are set to ‘1’, the GT-64010A assumes Little-endian data format and NO byte swapping is
done within the device.
13.1.2. Nomenclature
W
- Word, 32 bit data. (R4600 terminology)
DW
- Double-Word, 64 bit data. (R4600 terminology)
Even address - address of which A[2] == 0. In little-endian format this address points to
the LEAST significant W of a DW, in Big-endian format this address points to
the MOST significant W of a DW.
Odd address - address of which A[2] == 1. In little-endian format this address points to
the MOST significant W of a DW, in Big-endian format this address points to
the LEAST significant W of a DW.
Even word
- LEAST significant W of a DW.
Odd word
- MOST significant W of a DW
a) Bit 12 of the CPU Interface unit’s mode register (0x000) affects the following:
a1) Set to ‘1’ (Little-endian mode)
- No byte swapping within the CPU Interface unit on any data transfer.
a2) Set to ‘0’ (Big-endian mode)
- Byte swapping of data transfers to/from GT-64010A internal registers (including Configuration Data register,
0xcfc).
- No byte swapping of data transfers of which the source/target is external.
b) Bit 0 of the PCI Interface unit’s command register (0xc00) affects the following:
b1) Set to ‘1’ (No byte swapping)
- No byte swapping within the PCI Interface unit of any data transfer.
b2) Set to ‘0’ (Byte swapping)
- No byte swapping of data transfers to/from PCI Interface unit’s internal registers.
- Byte swapping of data transfers of which the source/target is external
c) Here is a table which describes all combinations of the resources and swapping
bits with a sample data. (‘CPU bit’ means the CPU Interface unit’s mode register
(0x000) bit 12, ‘PCI bit’ means the PCI Interface unit’s command register (0xc00)
bit 0). The sample data is 04030201h.
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