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参数资料
| 型号： | GTLP16612MTD |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 1/9页 |
| 文件大小： | 0K |
| 描述： | IC UNIV BUS TXRX 18BIT 56TSSOP |
| 标准包装： | 34 |
| 系列： | 74GTLP |
| 逻辑类型： | 通用总线收发器 |
| 电路数： | 18 位 |
| 输出电流高，低： | 32mA，32mA |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
2001 Fairchild Semiconductor Corporation
DS012390
www.fairchildsemi.com
March 1995
Revised March 2001
GTLP166
12
18-
Bit
T
TL/GTLP
U
n
iver
sal
Bus
T
ranscei
ver
GTLP16612
18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver
which provides TTL to GTLP signal level translation. The
device is designed to provide a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (
<1V), reduced input threshold levels and output
edge rate control which minimizes signal settling times.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different driver
output levels and receiver threshold. GTLP output low volt-
age is typically less than 0.5V, the output high is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic
levels
s Designed with an edge rate control circuit to reduce
output noise on GTLP port
s VREF pin provides external supply reference voltage for
receiver threshold adjustability
s Special
PVT
compensation
circuitry
to
provide
consistent performance over variations of process,
supply voltage and temperature
s TTL compatible Driver and Control inputs
s Designed using Fairchild advanced CMOS technology
s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down and power off high impedance for live
insertion
s 5V tolerant inputs and outputs on LVTTL port
s Open drain on GTLP to support wired-or connection
s Flow-through pinout optimizes PCB layout
s D-type flip-flop, latch and transparent data paths
s A Port outputs source/sink
32 mA/+32 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
GTLP16612MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
GTLP16612MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GTLP16612MTD_Q | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| GTLP16612MTDX | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| GTLP16616 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:17-Bit TTL/GTLP Bus Transceiver with Buffered Clock |
| GTLP16616B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| GTLP16616MEA | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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