参数资料
型号: GTLP16612MTD
厂商: Fairchild Semiconductor
文件页数: 7/9页
文件大小: 0K
描述: IC UNIV BUS TXRX 18BIT 56TSSOP
标准包装: 34
系列: 74GTLP
逻辑类型: 通用总线收发器
电路数: 18 位
输出电流高,低: 32mA,32mA
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 56-TSSOP
包装: 管件
7
www.fairchildsemi.com
GTLP166
12
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
CL includes probes and jig capacitance.
Test Circuit for B Outputs
CL includes probes and jig capacitance.
For B Port outputs, CL = 30 pF is used for
worst case edge rate.
Voltage Waveforms Pulse Duration
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Setup and Hold Times
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay Times
(A Port to B Port)
Voltage Waveforms Propagation Delay Times
(B Port to A Port)
All input pulses have the following characteristics: frequency
= 10 MHz, t
r = tf = 2 ns, ZO = 50. The outputs are measured
one at a time with one transition per measurement.
Voltage Waveforms Enable and Disable Times (A Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics:
frequency
= 10 MHz, t
r = tf = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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GTLP16616MEA 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel