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参数资料
| 型号： | GTLP16612MTD |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | IC UNIV BUS TXRX 18BIT 56TSSOP |
| 标准包装： | 34 |
| 系列： | 74GTLP |
| 逻辑类型： | 通用总线收发器 |
| 电路数： | 18 位 |
| 输出电流高，低： | 32mA，32mA |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
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2
GTLP16612
Pin Descriptions
Connection Diagram
Functional Description
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A Port and control pins
operate at LVTTL or 5V TTL levels while the B Port operates at GTLP levels. The transceiver logic includes D-type latches
and D-type flip-flops to allow data flow in transparent, latched and clock mode.
The functional operation is described in the truth table below.
Truth Table
(Note 1)
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
Pin
Names
Description
OEAB
A-to-B Output Enable (Active LOW)
OEBA
B-to-A Output Enable (Active LOW)
CEAB
A-to-B Clock Enable (Active LOW)
CEBA
B-to-A Clock Enable (Active LOW)
LEAB
A-to-B Latch Enable (Transparent HIGH)
LEBA
B-to-A Latch Enable (Transparent HIGH)
CLKAB
A-to-B Clock Pulse
CLKBA
B-to-A Clock Pulse
VREF
GTLP Input Reference Voltage
A1–A18
A-to-B TTL Data Inputs or
B-to-A 3-STATE Outputs
B1–B18
B-to-A GTLP Data Inputs or
A-to-B Open Drain Outputs
Inputs
Output
Mode
CEAB
OEAB
LEAB
CLKAB
A
B
X
H
X
Z
Latched
LLL
H
X
B0(Note 2)
storage
LLLL
X
B0(Note 3)
of A data
X
L
H
X
L
Transparent
XL
H
X
H
LLL
↑
L
Clocked storage
LLL
↑
H
of A data
HL
L
X
B0(Note 3)
Clock inhibit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GTLP16612MTD_Q | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| GTLP16612MTDX | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| GTLP16616 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:17-Bit TTL/GTLP Bus Transceiver with Buffered Clock |
| GTLP16616B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| GTLP16616MEA | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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