
Section 6 Bus Controller
Rev. 4.00 Jan 26, 2006 page 200 of 938
REJ09B0276-0400
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from
ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
φ
T1
T2
T3
RD
Address bus
Data bus
T1
T2
T1
T2
T3
Ti
T2
T1
HWR
φ
RD
Address bus
Data bus
HWR
Bus cycle A Bus cycle B
Long buffer-off
time
Data
collision
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1)
External Address Space Access Immediately after DRAM Space Access: If a DRAM space
access is followed by a non-DRAM external access when
HWR and LWR have been selected as
the
UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted
regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the
operation.
This is done to prevent simultaneous changing of the
HWR and LWR signals used as UCAS and
LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to
the external device in the next cycle.
A T
i cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output
pins.
In the case of consecutive DRAM space access precharge cycles (T
p), the ICIS0 and ICIS1 bit
settings are invalid. In the case of consecutive reads between different areas, for example, if the
second access is a DRAM access, only a T
p cycle is inserted, and a Ti cycle is not. The timing in
this case is shown in figure 6.46.