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参数资料
| 型号： | HI5804 |
| 厂商： | Intersil Corporation |
| 英文描述： | 12-Bit, 5 MSPS A/D Converter |
| 中文描述： | 12位，5 MSPS的A / D转换 |
| 文件页数： | 10/11页 |
| 文件大小： | 64K |
| 代理商： | HI5804 |
10
HI5804
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below f
S
/2.
Transient Response
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Overvoltage Recovery
Overvoltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the difference between the two internal voltage references.
The bandwidth given is measured at the specified sampling
frequency.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (t
AP
)
Aperture delay is the time delay between the external sam-
ple command (the falling edge of the clock) and the time at
which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
AJ
)
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
H
)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
OD
)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
LAT
)
After the analog sample is taken, the digital data is output on
the bus after the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse. The
digital data lags the analog input sample by 3 clock cycles.
相关PDF资料 |
PDF描述 |
|---|---|
| HI5804EVAL | 12-Bit, 5 MSPS A/D Converter |
| HI5804KCB | 12-Bit, 5 MSPS A/D Converter |
| HI5812JIB | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| HI5812JIJ | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| HI5812JIP | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HI5804EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| hi5804kcb | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HI5805 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:12-Bit, 5MSPS A/D Converter |
| HI5805_05 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:12-Bit, 5MSPS A/D Converter |
| HI5805BIB | 功能描述:IC ADC 12-BIT 5MSPS 28-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
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