参数资料
| 型号： | HI5860IBZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/12页 |
| 文件大小： | 0K |
| 描述： | CONV D/A 12BIT 130MSPS 28-SOIC |
| 标准包装： | 1 |
| 设置时间： | 35ns |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 200mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 剪切带 (CT) |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 130M |
| 其它名称： | HI5860IBZ-TCT |
9
FN4654.7
February 6, 2008
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Consult Application Note 9853.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60ppm/°C drift coefficient over the full
temperature range of the converter. It is recommended that
a 0.1F capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (the
analog supply voltage) and the external reference driven into
REFIO, pin 17. The full scale output current of the converter
is a function of the voltage reference used and the value of
RSET. IOUT should be within the 2mA to 20mA range,
though operation below 2mA is possible, with performance
degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V (pin 18). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91k
Ω R
SET
resistor, then the input coding to output current will resemble
Table 1:
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single-ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. RLOAD (the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage is shown in
Equation 2:
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at 0V. The loading as shown in
Figure 1 will result in a 500mV signal at the output of the
transformer if the full scale output current of the DAC is set
to 20mA.
VOUT = 2 x IOUT x REQ where REQ is ~12.5Ω. Allowing the
center tap to float will result in identical transformer output,
however the output pins of the DAC will have positive DC
offset. Since the DAC’s output voltage compliance range is
-0.3V to +1.25V, the center tap may need to be left floating or
DC offset in order to increase the amount of signal swing
available. The 50
Ω load on the output of the transformer
represents the spectrum analyzer’s input impedance.
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D11-D0)
IOUTA (mA)
IOUTB (mA)
11 11111 11111
20
0
10 00000 00000
10
00 00000 00000
0
20
I
OUT Fu llS ca le
()
V
FSADJ
R
SET
----------------------
32
×
=
(EQ. 1)
V
OUT
I
OUT
R
LOAD
×
=
(EQ. 2)
PIN 21
PIN 22
100
Ω
HI5860
50
Ω
50
Ω
50
Ω
FIGURE 1.
IOUTB
IOUTA
VOUT = (2 x IOUT x REQ)V
REQ IS THE IMPEDANCE
LOADING EACH OUTPUT
SPECTRUM ANALYZER
50
Ω REPRESENTS THE
HI5860
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