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参数资料
| 型号： | HI7190EVAL |
| 厂商： | Intersil Corporation |
| 英文描述： | null24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | null24位，精度高，Σ-ΔA / D转换 |
| 文件页数： | 11/24页 |
| 文件大小： | 187K |
| 代理商： | HI7190EVAL |
1881
Digital Section Description
A block diagram of the digital section of the HI7190 is shown
in Figure 9. This section includes a low pass decimation fil-
ter, conversion controller, calibration logic, serial interface,
and clock generator.
Digital Filtering
One advantage of digital filtering is that it occurs after the
conversion process and can remove noise introduced during
the conversion. It can not, however, remove noise present on
the analog signal prior to the ADC (which an analog filter
can).
One problem with the modulator/digital filter combination is
that excursions outside the full scale range of the device
could cause the modulator and digital filter to saturate. This
device has headroom built in to the modulator and digital fil-
ter which tolerates signal deviations up to 33% outside of the
full scale range of the device. If noise spikes can drive the
input signal outside of this extended range, it is recom-
mended that an input analog filter is used or the overall input
signal level is reduced.
Low Pass Decimation Filter
The digital low-pass filter is a Hogenauer (sinc
3
) decimating
filter. This filter was chosen because it is a cost effective low
pass decimating filter that minimizes the need for internal
multipliers and extensive storage and is most effective when
used with high sampling or oversampling rates. Figure 10
shows the frequency characteristics of the filter where f
C
is
the -3dB frequency of the input signal and f
N
is the
programmed notch frequency. The analog modulator sends
a one bit data stream to the filter at a rate of that is
determined by:
f
MODULATOR
= f
OSC
/128
f
MODULATOR
= 78.125kHz for f
OSC
= 10MHz.
The filter then converts the serial modulator data into 40-bit
words for processing by the Hogenauer filter. The data is
decimated in the filter at a rate determined by the CODE
word FP10-FP0 (programed by the user into the Control
Register) and the external clock rate. The equation is:
f
NOTCH
= f
OSC
/(512 x CODE).
The Control Register has 11 bits that select the filter cutoff
frequency and the first notch of the filter. The output data
update rate is equal to the notch frequency. The notch fre-
quency sets the Nyquist sampling rate of the device while
the -3dB point of the filter determines the frequency spec-
trum of interest (f
S
). The FP bits have a usable range of 10
through 2047 where 10 yields a 1.953kHz Nyquist rate.
The Hogenauer filter contains alias components that reflect
around the notch frequency. If the spectrum of the frequency
of interest reaches the alias component, the data has been
aliased and therefore undersampled.
Filter Characteristics
Please note: We have recently discovered a performance
anomaly with the HI7190. The problem occurs when the
digital code for the notch filter is programmed within
certain frequencies. We believe the error is caused by
the calibration logic and the digital notch code NOT the
absolute frequency. The error is seen when the user
applies mid-scale (0V input, Bipolar mode). With this
input, the expected digital output should be mid-scale
(800000
h
). Instead, there is a small probability, of an
erroneous negative full scale (000000
h
)output. Refer to
Technical Brief TB348 for complete details.
The FP10 to FP0 bits programmed into the Control Register
determine the cutoff (or notch) frequency of the digital filter.
The allowable code range is 00A
H
. This corresponds to a
maximum and minimum cutoff frequency of 1.953kHz and
10Hz, respectively when operating at a clock frequency of
10MHz. If a 1MHz clock is used then the maximum and min-
imum cutoff frequencies become 195.3kHz and 1Hz, respec-
tively. A plot of the (sinx/x)
3
digital filter characteristics is
shown in Figure 10. This filter provides greater than 120dB
of 50Hz or 60Hz rejection. Changing the clock frequency or
the programming of the FP bits does not change the shape
of the filter characteristics, it merely shifts the notch fre-
quency. This low pass digital filter at the output of the con-
V
RHI
V
RLO
V
INHI
V
INLO
AV
DD
AV
SS
CURRENT
SOURCE
HI7190
RATIOMETRIC
CONFIGURATION
LOAD CELL
FIGURE 7. BURN-OUT CURRENT SOURCE CIRCUIT
M
SERIAL I/O
SDO
SDIO
SCLK
CS
DRDY
RESET
SYNC
OSC
2
OSC
1
MODULATOR
CLOCK
DIGITAL
FILTER
CALIBRATION
AND CONTROL
CLOCK
GENERATOR
FIGURE 8. DIGITAL SECTION BLOCK DIAGRAM
HI7190
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