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参数资料
| 型号： | HI7190EVAL |
| 厂商： | Intersil Corporation |
| 英文描述： | null24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | null24位，精度高，Σ-ΔA / D转换 |
| 文件页数： | 14/24页 |
| 文件大小： | 187K |
| 代理商： | HI7190EVAL |
1884
System Gain Calibration Mode
The Gain Calibration Mode is a single step process that
updates the Positive and Negative Full Scale Calibration Reg-
isters. This mode will convert the external differential signal
applied to the V
IN
inputs and then store that value in the Nega-
tive Full Scale Calibration Register. Then the polarity of the
input is reversed internally and another conversion is per-
formed. This conversion result is written to the Positive Full
Scale Calibration Register. The user must apply the +Full
Scale voltage to the HI7190 analog inputs and allow the signal
to settle before selecting this mode. After 1 more conversion
period the DRDY line will activate signaling the calibration is
complete and valid data is present in the data output register.
Reserved
This mode is not used in the HI7190 and should not be
selected. There is no internal detection logic to keep this
condition from being selected and care should be taken not
to assert this bit combination.
Offset and Span Limits
There are limits to the amount of offset and gain which can
be adjusted out for the HI7190. For both bipolar and unipolar
modes the minimum and maximum input spans are
0.2 x V
REF
/GAIN and 1.2 x V
REF
/GAIN respectively.
In the unipolar mode the offset plus the span cannot exceed
the 1.2 x V
REF
/GAIN limit. So, if the span is at its minimum
value of 0.2 x V
REF
/GAIN, the offset must be less than 1 x
V
REF
/GAIN. In bipolar mode the span is equidistant around
the voltage used for the zero scale point. For this mode the
offset plus half the span cannot exceed 1.2 x V
REF
/GAIN. If
the span is at
±
0.2 x V
REF
/GAIN
,
then the offset can not be
greater than
±
2 x V
REF
/GAIN.
Serial Interface
The HI7190 has a flexible, synchronous serial communication
port to allow easy interfacing to many industry standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola 6805/11 SPI and Intel 8051 SSR protocols. The
Serial Interface is a flexible 2-wire or 3-wire hardware interface
where the HI7190 can be configured to read and write on a
single bidirectional line (SDIO) or configured for writing on
SDIO and reading on the SDO line.
The interface is byte organized with each register byte
having a specific address and single or multiple byte trans-
fers are supported. In addition, the interface allows flexibility
as to the byte and bit access order. That is, the user can
specify MSB/LSB first bit positioning and can access bytes
in ascending/descending order from any byte position.
The serial interface allows the user to communicate with 5
registers that control the operation of the device.
Data Output Register
- a 24-bit, read only register
containing the conversion results.
Control Register
- a 24-bit, read/write register containing
the setup and operating modes of the device.
Offset Calibration Register
- a 24-bit, read/write register
used for calibrating the zero point of the converter or system.
Positive Full Scale Calibration Register
- a 24-bit,
read/write register used for calibrating the Positive Full Scale
point of the converter or system.
Negative Full Scale Calibration Register
- a 24-bit,
read/write register used for calibrating the Negative Full
Scale point of the converter or system.
Two clock modes are supported. The HI7190 can accept the
serial interface clock (SCLK) as an input from the system or
generate the SCLK signal as an output. If the MODE pin is
logic low the HI7190 is in external clocking mode and the
SCLK pin is configured as an input. In this mode the user
supplies the serial interface clock and all interface timing
specifications are synchronous to this input. If the MODE pin
is logic high the HI7190 is in self-clocking mode and the
SCLK pin is configured as an output. In self-clocking mode,
SCLK runs at F
SCLK
= OSC
1
/8 and stalls high at byte
boundaries. SCLK does NOT have the capability to stall low
in this mode. All interface timing specifications are
synchronous to the SCLK output.
Normal operation in self-clocking mode is as follows (See
Figure 13): CS is sampled low on falling OSC
1
edges. The
first SCLK transition output is delayed 29 OSC
1
cycles from
the next rising OSC
1
. SCLK transitions eight times and then
stalls high for 28 OSC
1
cycles. After this stall period is com-
pleted SCLK will again transition eight times and stall high.
This sequence will repeat continuously while CS is active.
The extra OSC
1
cycle required when coming out of the CS
inactive state is a one clock cycle latency required to prop-
erly sample the CS input. Note that the normal stall at byte
boundaries is 28 OSC
1
cycles thus giving a SCLK rising to
rising edge stall period of 32 OSC
1
cycles.
The affects of CS on the I/O are different for self-clocking
mode (MODE = 1) than for external mode (MODE = 0). For
external clocking mode CS inactive disables the I/O state
machine, effectively freezing the state of the I/O cycle. That
is, an I/O cycle can be interrupted using chip select and the
HI7190 will continue with that I/O cycle when re-enabled via
CS. SCLK can continue toggling while CS is inactive. If CS
goes inactive during an I/O cycle, it is up to the user to
ensure that the state of SCLK is identical when reactivating
CS as to what it was when CS went inactive. For read opera-
tions in external clocking mode, the output will go three-state
immediately upon deactivation of CS.
For self-clocking mode (MODE = 1), the affects of CS are
different. If CS transitions high (inactive) during the period
when data is being transferred (any non stall time) the HI7190
will complete the data transfer to the byte boundary. That is,
once SCLK begins the eight transition sequence, it will always
complete the eight cycles. If CS remains inactive after the byte
has been transferred it will be sampled and SCLK will remain
stalled high indefinitely. If CS has returned to active low before
the data byte transfer period is completed the HI7190 acts as
if CS was active during the entire transfer period.
HI7190
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