参数资料
型号: HIP6004BCB-T
厂商: Intersil
文件页数: 14/15页
文件大小: 0K
描述: IC CTRLR PWM VOLTAGE MON 20-SOIC
标准包装: 1,000
应用: 控制器,Intel Pentium?,II,Pro
输入电压: 5V,12V
输出数: 1
输出电压: 1.3 V ~ 3.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 带卷 (TR)
HIP6004B
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
E1
E
0.25(0.010) M
GAUGE
B M
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INCHES MILLIMETERS
-B-
PLANE
SYMBOL
MIN
MAX
MIN
MAX
NOTES
1
2
3
L
A
A1
-
0.002
0.047
0.006
-
0.05
1.20
0.15
-
-
-A-
0.05(0.002)
D
SEATING PLANE
A
0.25
0.010
A2
b
c
0.031
0.0075
0.0035
0.051
0.0118
0.0079
0.80
0.19
0.09
1.05
0.30
0.20
-
9
-
e
b
0.10(0.004) M
-C-
C A M
B S
A1
α
0.10(0.004)
A2
c
D
E1
e
E
L
0.252 0.260
0.169 0.177
0.026 BSC
0.246
0.256
0.0177
0.0295
6.40 6.60
4.30 4.50
0.65 BSC
6.25
6.50
0.45
0.75
3
4
-
-
6
N
20
20
7
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
α
0 o
8 o
0 o
8 o
-
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
14
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