参数资料
型号: HIP6018
厂商: Intersil Corporation
元件分类: FPGA
英文描述: FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 先进的双PWM和线性功率控制
文件页数: 6/14页
文件大小: 133K
代理商: HIP6018
2-229
Functional Pin Description
VSEN1 (Pin 19)
This pin is connected to the PWM converter’s output voltage.
The PGOOD and OVP comparator circuits use this signal to
report output voltage status and for over voltage protection.
OCSET1 (Pin 20)
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET. R
OCSET
, an internal 200
μ
A current source
(I
OCSET
), and the upper MOSFET on-resistance (r
DS(ON)
)
set the PWM converter over-current (OC) trip point
according to the following equation:
I
DS ON
)
An over-current trip cycles the soft-start function. Sustaining
an over-current for 2 soft-start intervals shuts down the
controller.
SS (Pin 9)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 11
μ
A (typically) current source, sets
the soft-start interval of the converter.
Pulling this pin low with an open drain signal will shut down
the IC.
VID0, VID1, VID2, VID3, VID4 (Pins 6, 5, 4, 3 and 2)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the core converter
output voltage. It also sets the core PGOOD and OVP
thresholds.
COMP1 and FB1 (Pins 17 and 18)
COMP1 and FB1 are the available external pins of the PWM
error amplifier. The FB1 pin is the inverting input of the error
amplifier. Similarly, the COMP1 pin is the error amplifier
output. These pins are used to compensate the voltage-
control feedback loop of the PWM converter.
GND (Pin 14)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
PGOOD (Pin 7)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
core output is not within
±
10% of the DACOUT reference
voltage and the other outputs are below their under-voltage
thresholds.
The PGOOD output is open for VID codes that inhibit
operation. See Table 1.
PHASE1 (Pin 23)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin is used to monitor the voltage
drop across the upper MOSFET for over-current protection.
UGATE1 (Pin 24)
Connect UGATE pin to the PWM converter’s upper MOSFET
gate. This pin provides the gate drive for the upper MOSFET.
PGND (Pin 21)
This is the power ground connection. Tie the PWM
converter’s lower MOSFET source to this pin.
LGATE1 (Pin 22)
Connect LGATE1 to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.
VCC (Pin 1)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC.
RT (Pin 10)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
T
) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Conversely, connecting a pull-up resistor (R
T
) from this pin
to VCC reduces the switching frequency according to the
following equation:
7
T
FAULT (Pin 8)
This pin is low during normal operation, but it is pulled to
VCC in the event of an over-voltage or over-current
condition.
DRIVE3 (Pin 15)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the linear controller’s pass transistor.
FB3 (Pin 16)
Connect this pin to a resistor divider to set the linear
controller output voltage.
VOUT2 (Pin 13)
Output of the linear regulator. Supplies current up to 230mA.
FB2 (Pin 11)
Connect this pin to a resistor divider to set the linear
regulator output voltage.
I
PEAK
R
×
---------------------------------------------------
=
Fs
200kHz
T
6
)
--------------------
+
(R
T
to GND)
Fs
200kHz
--------------------
)
(R
T
to 12V)
HIP6018
相关PDF资料
PDF描述
HIP6018CB Advanced PWM and Dual Linear Power Control
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