参数资料
型号: HIP6301VCB
厂商: Intersil
文件页数: 14/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-SOIC
标准包装: 38
PWM 型: 控制器
输出数: 4
频率 - 最大: 336kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
HIP6301V, HIP6302V
Droop, Selection of R IN
effects, such as series resistance, the peak-to-peak value of
V IN ( V CORE ) – V CORE
( L ) ( F SW ) ( V IN )
The average of the currents detected through the R ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R IN , so the average
current creates a voltage drop across R IN . This drop
the sawtooth current can be described by Equation 4.
2
I P – P = -----------------------------------------------------------------
(EQ. 4)
increases the apparent V CORE voltage with increasing load
current, causing the system to decrease V CORE to maintain
balance at the FB pin. This is the desired “droop” voltage
used to maintain V CORE within limits under transient
Where: V CORE
V IN
L
F SW
= DC value of the output or V ID voltage
= DC value of the input or supply voltage
= value of the inductor
= switching frequency
conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient.
In order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the
range when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter
components.
R IN should be selected to give the desired “droop” voltage at
the normal full load current 50μA applied through the R ISEN
resistor (or at a different full load current if adjusted as in
Example: For V CORE = 1.6V,
V IN = 12V,
L = 1.3μH,
F SW = 250kHz,
Then I P-P = 4.3A
25
20
15
10
5
R IN = Vdroop ? ( 50 μ A )
For a Vdroop of 80mV, R IN = 1.6k Ω
(EQ. 3)
0
The AC feedback components, R FB and Cc, are scaled in
relation to R IN .
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of all
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
r DS(ON) between synchronous rectifiers. If a FET has a
higher r DS(ON) , the current through that phase will be
reduced.
Figures 10 and 11 show the inductor current of a 2-phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multiphase buck
converter has two components. There is a current equal to
the load current divided by the number of phases (I LT /n), and
a sawtooth current, (I P-P ) resulting from switching. The
sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
14
FIGURE 10. TWO CHANNEL MULTIPHASE SYSTEM
WITH CURRENT BALANCING DISABLED
25
20
15
10
5
0
FIGURE 11. TWO CHANNEL MULTIPHASE SYSTEM
WITH CURRENT BALANCING ENABLED
The inductor, or load current, flows alternately from V IN
through Q 1 and from ground through Q 2 . The controller
samples the on-state voltage drop across each Q 2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, 1/F SW , after Q 1 is
FN9034.3
May 5, 2008
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