参数资料
型号: HIP6500BEVAL1
厂商: Intersil Corporation
元件分类: 基准电压源/电流源
英文描述: Multiple Linear Power Controller with ACPI Control Interface
中文描述: 多重线性电源控制器ACPI控制接口
文件页数: 9/15页
文件大小: 156K
代理商: HIP6500BEVAL1
9
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10
μ
A current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figure 9 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10
μ
A current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the 3.3V
SB
error amplifiers’ reference input starts its transition, causing
the output voltage to ramp up proportionally. The ramp-up
continues until time T3 when the 3.3V
SB
voltage reaches the
set value. After the 3.3V
SB
reached its set value, as the soft-
start capacitor voltage reaches approximately 2.75V, the
under-voltage monitoring circuit of this output is activated
and the soft-start capacitor is quickly discharged to
approximately 1.25V. Following the 3ms (typical) time-out
between T3 and T4, the memory and enabling pins’
selection are latched in, and the soft-start capacitor
commences a second ramp-up designed to smoothly bring
up the remainder of the voltages required by the system. At
time T5 all voltages are within regulation limits, and as the
SS voltage reaches 2.75V, all the UV monitors are activated
and the SS capacitor is quickly discharged to 1.25V, where it
remains until the next transition.
FIGURE 8. 2.5/3.3V
MEM
, 3.3V
SB
AND VCLK TIMING DIAGRAM
5VSB
12V
S3
S5
DRV2
DEVICE
VSEN2
INTVSEN2
3V3SB
VCLK
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE
(ALL OUTPUTS ENABLED)
0V
0V
TIME
SOFT-START
(1V/DIV)
OUTPUT
VOLTAGES
(1V/DIV)
V
OUT3
(3.3V
DUAL
)
V
OUT2
(2.5V
MEM
)
V
OUT5
(5V
DUAL
)
T1 T2
T3
T0
5VSB
(1V/DIV)
T5
T4
V
OUT1
(3.3V
SB
)
V
OUT4
(2.5V
CLK
)
FIGURE 10. SOFT-START INTERVAL IN ACTIVE STATE
(2.5/3.3V
MEM
OUTPUT SHOWN IN 2.5V SETTING)
0V
0V
TIME
OUTPUT
VOLTAGES
(1V/DIV)
T1
T2
T3
T0
INPUT VOLTAGES
(2V/DIV)
+5V
IN
+12V
IN
+5VSB
V
OUT2, 4
V
OUT3
(3.3V
DUAL
)
V
OUT1
(3.3V
SB
)
V
OUT5
(5V
DUAL
)
DLA PIN
(2V/DIV)
SOFT-START
(1V/DIV)
(2.5V
MEM
, 2.5V
CLK
)
+3.3V
IN
HIP6500B
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