参数资料
| 型号： | HIP6500BEVAL1 |
| 厂商： | Intersil |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD HIP6500 |
| 标准包装： | 1 |
| 类型： | ACPI 控制器 |
| 适用于相关产品： | HIP6500B |
| 所含物品： | 完全组装的评估板 |
Application Note 9862
State Transitions
Figure 6 shows the transition from active state (S0, S1) to S3
sleep state on the HIP6500BEVAL1 board. Prior to time T0,
the evaluation board was operating in active mode, with SW1
on and SW2 and SW3 off. At time T0, SW2 is switched on,
5V DUAL
triggering the turn-off of the ATX and the switch-over of the
output regulation from the active ATX output rails to the 5VSB
supply. Very shortly after time T0, the ATX responds to the
turn-off request, and the 5V input starts to ramp down under
the current drawn by the embedded 5 Ω serpentine resistor.
As it can be noticed in the scope capture, the transitions are
devoid of any perturbations. These smooth transitions are
desirable in a computer system, power glitches being the
leading cause of power-related system crashes.
GND>
3.3V DUAL/SB
3.3V MEM
2ms/DIV
5VIN
2.5V MEM
2.5V CLK
T0
FIGURE 7. HIP6502BEVAL1 ACTIVE STATE (S0, S1) TO
3.3V DUAL
3.3V SB
5VIN
2.5V MEM
5V DUAL
2.5V CLK
STANDBY STATE (S3) TRANSITION WITH ALL
OUTPUTS ENABLED
Figure 8 highlights the transition back from S3 sleep state to
active state (S0, S1) with all outputs enabled, as captured on
the HIP6500BEVAL1 board. At time T0, SW2 is switched off,
enabling the main ATX outputs. As 3.3VIN, 5VIN, and 12VIN
exceed their undervoltage thresholds, the 25ms timer
internal to the HIP6500B is initiated. At T1 the time-out
GND>
2ms/DIV
expires, conduction on the 3.3V DUAL and 5V DUAL outputs is
transferred to the N-MOS switches and the 2.5V CLK output
begins its ramp-up. At time T2, all the outputs are functional
T0
FIGURE 6. HIP6500BEVAL1 ACTIVE STATE (S0, S1) TO
STANDBY STATE (S3) TRANSITION WITH ALL
OUTPUTS ENABLED
Figure 7 shows the transition from active state (S0, S1) to S3
sleep state on the HIP6502BEVAL1 board. Similarly, this
board mirrors the functionality and benefits of the
HIP6500BEVAL1.
and ready for active state operation. The 2.5V MEM output is
maintained glitch-free throughout the input voltage transition
from the standby to the main ATX outputs.
5V DUAL
5VIN
3.3V DUAL
3.3V SB
2.5V MEM
2.5V CLK
GND>
10ms/DIV
T0
T1
T2
FIGURE 8. HIP6500BEVAL1 STANDBY STATE (S3) TO
ACTIVE STATE (S0, S1) TRANSITION WITH ALL
OUTPUTS ENABLED
5
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