参数资料
型号: HIP6500BEVAL1
厂商: Intersil
文件页数: 6/20页
文件大小: 0K
描述: EVALUATION BOARD HIP6500
标准包装: 1
类型: ACPI 控制器
适用于相关产品: HIP6500B
所含物品: 完全组装的评估板
Application Note 9862
Figure 9 highlights the transition from S5 sleep state to
active state (S0, S1) with no outputs enabled (3.3V SB is
always enabled), as captured on the HIP6500BEVAL1
board. At time T0, SW2 is switched off, enabling the main
2.5V>
2.5V MEM
50mV/DIV
ATX outputs. As 3.3VIN, 5VIN, and 12VIN exceed their
undervoltage thresholds (5VIN shown, only), the 25ms timer
internal to the HIP6500B is initiated and similar to the start-
up shown in Figure 8, the 3V DUAL and 5V DUAL outputs
undergo a quasi-soft-start as conduction takes place through
0A>
2.00A/DIV
the body diodes of the pass NMOS switches. At T1 the time-
out expires, conduction on the 3.3V DUAL and 5V DUAL
outputs is transferred to the N-MOS switches and the
2.5V CLK and 2.5V MEM outputs begin their ramp-up. At time
T2, all the outputs are functional and ready for active state
operation.
2.5V>
0A>
2.5V CLK
100 μ s/div
50mV/DIV
500mA/div
FIGURE 10. HIP6500BEVAL1 ACTIVE STATE (S0, S1) OUTPUT
TRANSIENT RESPONSE
5VIN
In Figure 11, the outputs shown are separately subjected to
5V DUAL
3.3V SB
load transients while operating in active state (S0, S1).
Transient loading of the outputs is as follows:
3.3V DUAL
2.5V CLK
2.5V MEM
- 3.3V DUAL : 500mA to 3.2A at 0.2A/ μ s
- 5V DUAL : 200mA to 2.5A at 0.1A/ μ s
3.3V DUAL
3.3V>
200mV/DIV
GND>
10ms/DIV
T0
T1
T2
FIGURE 9. HIP6500BEVAL1 STANDBY STATE (S5) TO
ACTIVE STATE (S0, S1) TRANSITION WITH NO
0A>
2.0A/DIV
OUTPUTS ENABLED
5.0V>
5V DUAL
200mV/DIV
The 25ms time-out employed by the HIP6500B (and
HIP6502B) is necessary in order to insure that the main ATX
outputs are allowed to stabilize and reach regulation limits
0A>
2.0A/DIV
before any circuits are connected to, or are allowed to derive
their voltages from them. This technique insures glitch-free
operation, compatible with virtually any ATX power supply.
Transient Response
Given the similarity of the two evaluation boards, only
HIP6500BEVAL1 results are shown in Figures 10-12; the
respective outputs of the HIP6502BEVAL1 exhibit similar
performance. All outputs shown in the oscilloscope captures
are DC offset by their nominal value and are DC coupled.
The current waveforms underneath each of the output
voltage waveforms show the (transient) current drawn from
the respective output.
In Figure 10, the outputs shown are separately subjected to
load transients while operating in active state (S0, S1).
Transient loading of the outputs is as follows:
- 2.5V MEM : 500mA to 3.2A at 1A/ μ s
- 2.5V CLK : 180mA to 700mA at 0.1A/ μ s
6
500 μ s/DIV
FIGURE 11. HIP6500BEVAL1 ACTIVE STATE (S0, S1) OUTPUT
TRANSIENT RESPONSE
The 3.3V DUAL and 5V DUAL outputs closely follow the AC
meandering of the ATX 3.3V and 5V outputs, being
separated only by the r DS(ON) of the N-MOS switches (Q4
and Q6). During the transient loading, the 3.3V DUAL output
develops a DC offset (compared to the ATX 3.3V), due to
the voltage droop across Q4. Specific to this circuit and the
particular circuit loading, the offset can easily be identified as
the product of the r DS(ON) of the pass transistor and the
output current. A similar explanation accompanies the
5V DUAL output waveform.
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