参数资料
| 型号： | HIP6501ACB-T |
| 厂商： | Intersil |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | IC PWM TRIPLE POWER CTRLR 16SOIC |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 电源电压： | 5V，12V |
| 电流 - 电源： | 20mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
HIP6501A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5VDUAL SWITCH CONTROLLER (V OUT3 )
5VDL Under-Voltage Rising Threshold
5VDL Under-Voltage Hysteresis
-
-
3.750
260
-
-
V
mV
5VDLSB Output Drive Current
5VDLSB Pull-up Impedance to 5VSB
I 5VDLSB
5VDLSB = 4V
-20
-
-
350
-40
-
mA
?
TIMING INTERVALS
Active State Assessment Past 12V
Note 2
40
50
60
ms
Threshold
Maximum Allowable S3 to S5 Skew
5VSB POR Extension Past Threshold
-
-
200
3.3
-
-
μ s
ms
Voltage
CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT)
High Level Threshold
Low Level Threshold
S3,S5 Internal Pull-up Impedance to 5VSB
-
0.8
-
-
-
70
2.2
-
-
V
V
k ?
FAULT Output Impedance
FAULT Under-Voltage Reporting Delay
FAULT = high
-
-
100
10
-
-
?
μ s
TEMPERATURE MONITOR
Fault-Level Threshold
Shutdown-Level Threshold
Note 3
Note 3
125
-
-
150
-
-
°C
°C
NOTES:
2. Guaranteed by Correlation.
3. Guaranteed by Design.
Functional Pin Description
5VSB (Pin 1)
Provide a 5V bias supply for the IC to this pin by connecting
it to the ATX 5VSB output. This pin also provides the base
bias current for all the external NPN transistors controlled by
the IC. The voltage at this pin is monitored for power-on
reset (POR) purposes.
GND (Pin 8)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
S3 and S5 (Pins 6 and 7)
These pins switch the IC’s operating state from active (S0,
S1) to S3 and S4/S5 sleep states. Connect S3 to SLP_S3
and S5 to SLP_S5. These are digital inputs featuring internal
70k ? (typical) resistor pull-ups to 5VSB. Internal circuitry de-
glitches the S3 pin for disturbances. Additional circuitry
blocks any illegal state transitions (such as S3 to S4/S5 or
vice versa). When entering an S4/S5 sleep state, the S3
signal is allowed to go low as far as 200 μ s (typically) ahead
of the S5 signal.
5
EN3VDL and EN5VDL (Pins 2 and 5)
These pins control the logic governing the output behavior in
response to S3 and S4/S5 requests. These are digital inputs
whose status can only be changed during active states
operation or during chip shutdown (SS pin grounded by
external open-drain device). The input information is
latched-in when entering a sleep state, as well as following
5VSB POR release or exit from shutdown.
FAULT/MSEL (Pin 9)
This is a multiplexed function pin allowing the setting of the
memory output voltage to either 2.5V or 3.3V (for RDRAM or
SDRAM memory systems). The memory voltage setting is
latched-in 3ms (typically) after 5VSB POR release. In case
of an under-voltage on any of the outputs or an over-
temperature event, this pin is used to report the fault
condition by being pulled to 5VSB.
SS (Pin 13)
Connect a small ceramic capacitor (allowable range: 5nF-
0.22 μ F; 0.1 μ F recommended) from this pin to GND. The
internal Soft-Start (SS) current source along with the
external capacitor creates a voltage ramp used to control the
ramp-up of the output voltages. Pulling this pin low with an
open-drain device shuts down all the outputs as well as
FN4749.6
December 30, 2004
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