参数资料
| 型号： | HIP6501ACB-T |
| 厂商： | Intersil |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC PWM TRIPLE POWER CTRLR 16SOIC |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 电源电压： | 5V，12V |
| 电流 - 电源： | 20mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
HIP6501A
Soft-Start Circuit
5VSB
S3
S5
12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 6. 3V DUAL AND 5V DUAL TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 1
5VSB
S3
S5
12V
3V3DLSB
DLA
Soft-Start into Sleep States (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10 μ A current source charges an external capacitor
to 5V. The error amplifiers reference inputs are clamped to a
level proportional to the SS (Soft-Start) pin voltage. As the
SS pin voltage slews from about 1.25V to 2.5V, the input
clamp allows a rapid and controlled output voltage rise.
Figure 9 shows the soft-start sequence for the typical
application start-up in a sleep state with all output voltages
enabled. At time T0 5V SB (bias) is applied to the circuit. At
time T1, 5V SB surpasses POR level, and an internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V. At this point, the 10 μ A current source
continues the charging up to T2, where a voltage of 1.25V
(typically) is reached and an internal clamp limits further
charging. Clamping of the soft-start voltage (T2 to T3
interval) should only be noticed with capacitors smaller than
0.1 μ F; soft-start capacitors of 0.1 μ F and above should
present a soft-start ramp void of this plateau. At time T3,
3ms (typically) past the 5V SB POR (T1), the memory output
voltage selection is latched in and the charging of the soft-
start capacitor resumes, using the 10 μ A current source. At
this point, the error amplifiers’ reference inputs are starting
their transitions, causing the output voltages to ramp up
proportionally. The ramping continues until time T4 when all
the voltages reach the set value. At time T5, when the soft-
start capacitor value reaches approximately 2.8V, the under-
voltage monitoring circuits are activated and the soft-start
capacitor is quickly discharged down to the value attained at
time T2 (approximately 1.25V).
3V3DL
5VDLSB
5VSB
5VDL
FIGURE 7. 3V DUAL AND 5V DUAL TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 0
5VSB
S3
0V
(1V/DIV)
OUTPUT
SOFT-START
(1V/DIV)
UV DETECT ENABLE
(LOGIC LEVEL)
V OUT3 (5V DUAL )
S5
12V
INTERNAL
VSEN2
DEVICE
VOLTAGES
(1V/DIV)
V OUT1 (3.3V DUAL )
V OUT2 (2.5V MEM )
DRV2
VSEN2
FIGURE 8. 2.5/3.3V MEM TIMING DIAGRAM
8
0V
T0 T1 T2 T3 T4 T5
TIME
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL
OUTPUTS ENABLED)
FN4749.6
December 30, 2004
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| HIP6501ACBZ | 功能描述:PMIC 解决方案 COMPANION CHIP TO HI6020/21 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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