参数资料
型号: HM-6516883
厂商: Intersil Corporation
英文描述: 2K x 8 CMOS RAM
中文描述: 2K × 8 CMOS存储器
文件页数: 4/8页
文件大小: 201K
代理商: HM-6516883
176
TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
HM-6516B/883
HM-6516/883
MIN
MAX
MIN
MAX
Chip Enable
Access Time
(1)
TELQV
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
200
ns
Address Access
Time
(2)
TAVQV
VCC = 4.5 and 5.5V,
(Note 3)
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
200
ns
Chip Enable
Pulse Negative
Width
(9)
TELEH
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
ns
Chip Enable
Pulse Positive
Width
(10)
TEHEL
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
50
-
80
-
ns
Address Set-up
Time
(11)
TAVEL
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
ns
Address Hold
Time
(12)
TELAX
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
30
-
50
-
ns
Write Enable
Pulse Width
(13)
TWLWH
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
ns
Write Enable
Pulse Set-up
Time
(14)
TWLEH
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
ns
Chip Selection to
End of Write
(15)
TELWH
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
ns
Data Set-up Time
(16)
TDVWH
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
50
-
80
-
ns
Data Hold Time
(17)
TWHDX
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
10
-
10
-
ns
Read or Write
Cycle Time
(18)
TELEL
VCC = 4.5 and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
170
-
280
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-6516/883
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