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参数资料
| 型号： | HM-6516883 |
| 厂商： | Intersil Corporation |
| 英文描述： | 2K x 8 CMOS RAM |
| 中文描述： | 2K × 8 CMOS存储器 |
| 文件页数： | 6/8页 |
| 文件大小： | 201K |
| 代理商： | HM-6516883 |
178
Timing Waveforms
The address information is latched in the on-chip registers on
the falling edge of E (T = 0), minimum address setup and hold
time requirements must be met. After the required hold time,
the addresses may change state without affecting device oper-
ation. During time (T = 1), the outputs become enabled but data
is not valid until time (T = 2), W must remain high throughout
the read cycle. After the data has been read, E may return high
(T = 3). This will force the output buffers into a high impedance
mode at time (T = 4). G is used to disable the output buffers
when in a logical “1” state (T = -1, 0, 3, 4, 5). After (T = 4) time,
the memory is ready for the next cycle.
The write cycle is initiated on the falling edge of E (T = 0), which
latches the address information in the on-chip registers. If a
write cycle is to be performed where the output is not to
become active, G can be held high (inactive). TDVWH and
TWHDX must be met for proper device operation regardless of
G. If E and G fall before W falls (read mode), a possible bus
conflict may exist. If E rises before W rises, reference data
setup and hold times to the E rising edge. The write operation
is terminated by the first rising edge of W (T = 2) or E (T = 3).
After the minimum E high time (TEHEL), the next cycle may
begin. If a series of consecutive write cycles are to be per-
formed, the W line may be held low until all desired locations
have been written. In this case, data setup and hold times
must be referenced to the rising of E.
HIGH
NEXT
(11)
TAVEL
(12)
TELAX
ADD
(5)
TEHQZ
VALID DATA OUT
(5)
TEHQZ
(8)
TGHQZ
(7) TGLQX
A
E
W
DQ
G
TIME
REFERENCE
-1
0
1
2
3
4
5
(2) TAVQV
(11)
TAVEL
(18) TELEL
(9) TELEH
(10) TEHEL
(10) TEHEL
(1) TELQV
TELQX
(5)
(6) TGLQV
FIGURE 1. READ CYCLE
VALID ADD
(11)
TAVEL
(12)
TELAX
(11)
TAVEL
(17)
TWHDX
HIGH
A
E
W
DQ
G
TIME
REFERENCE
-1
0
1
2
3
4
5
VALID ADD
NEXT ADD
(18) TELEL
(10) TEHEL
(10) TEHEL
(9) TELEH
(13) TWLWH
(14) TWLEH
(16)
TDVWH
FIGURE 2. WRITE CYCLE
(15)
TELWH
VALID DATA IN
HM-6516/883
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HM-6518 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:1024 x 1 CMOS RAM |
| HM-6518/883 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:1024 x 1 CMOS RAM |
| HM-6518883 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:1024 x 1 CMOS RAM |
| HM651R5 | 制造商:TT Electronics / BI Technologies 功能描述:HI CURRENT LOW PROFILE SMT INDUCTOR |
| HM65-1R5LF | 制造商:BITECH 制造商全称:Bi technologies 功能描述:High Current Low Profile Surface Mount Inductors |
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