- 您现在的位置：买卖IC网 > PDF目录299181 > HM5165405LTT-5 (ELPIDA MEMORY INC) 16M X 4 EDO DRAM, 50 ns, PDSO32 PDF资料下载
参数资料
| 型号： | HM5165405LTT-5 |
| 厂商： | ELPIDA MEMORY INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 4 EDO DRAM, 50 ns, PDSO32 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-32 |
| 文件页数： | 7/35页 |
| 文件大小： | 377K |
| 代理商： | HM5165405LTT-5 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
HM5164405 Series, HM5165405 Series
15
Self Refresh Mode (L-version)
HM5164405L/HM5165405L
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
5$6 pulse width (self refresh)
t
RASS
100
—
100
—
s
26
5$6 precharge time (self refresh)
t
RPS
90
—
110
—
ns
26
&$6 hold time (self refresh)
t
CHS
–50
—
–50
—
ns
Notes: 1. AC measurements assume t
T = 2 ns.
2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
5$6-only refresh or &$6-before-5$6 refresh).
3. Operation with the t
RCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if t
RCD is greater than the specified tRCD (max) limit, than the access time is
controlled exclusively by t
CAC.
4. Operation with the t
RAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if t
RAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by t
AA.
5. Either t
OED or tCDD must be satisfied.
6. Either t
DZO or tDZC must be satisfied.
7. V
IH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between V
IH (min) and VIL (max).
8. Assumes that t
RCD ≤ tRCD (max) and tRAD ≤ tRAD (max).
If t
RCD or tRAD is greater than the maximum
recommended value shown in this table, t
RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t
RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that t
RAD ≥ tRAD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
12. Either t
RCH or tRRH must be satisfied for a read cycles.
13. t
OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. t
WCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters.
They are included in the
data sheet as electrical characteristics only; if t
WCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥ t
RWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥
t
CPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15. t
DS and tDH are referred to &$6 leading edge in early write cycles and to :( leading edge in
delayed write or read-modify-write cycles.
16. t
RASP defines 5$6 pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t
AA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles,
2( must disable output buffer prior to applying
data to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC/VSS line noise, which causes to degrade VIH min/VIL max
level.
相关PDF资料 |
PDF描述 |
|---|---|
| HM5165805FLJ-5 | 8M X 8 EDO DRAM, 50 ns, PDSO32 |
| HM51S4265DTT-6 | 256K X 16 EDO DRAM, 60 ns, PDSO40 |
| HM55-21R47 | 1 ELEMENT, 0.47 uH, GENERAL PURPOSE INDUCTOR |
| HM628127HLJP-25 | 128K X 8 STANDARD SRAM, 25 ns, PDSO32 |
| HM62W8128DLR-7 | STANDARD SRAM, PDSO32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HM51680J | 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL |
| HM51-680J | 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL |
| HM51-680JLF | 制造商:BITECH 制造商全称:Bi technologies 功能描述:Axially Leaded Miniature Power Inductors |
| HM51680K | 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL |
| HM51-680K | 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL |
发布紧急采购，3分钟左右您将得到回复。