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参数资料
| 型号： | HM5165405LTT-5 |
| 厂商： | ELPIDA MEMORY INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 4 EDO DRAM, 50 ns, PDSO32 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-32 |
| 文件页数： | 8/35页 |
| 文件大小： | 377K |
| 代理商： | HM5165405LTT-5 |
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HM5164405 Series, HM5165405 Series
16
20. t
HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
5$6 cycle (EDO
page mode mix cycle (1), (2)), minimum value of
&$6 cycle (t
CAS + tCP + 2 tT) becomes greater
than the specified t
HPC (min) value.
The value of
&$6 cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of
5$6 and &$6.
Hold time and turn off time are specified by the timing specifications of later rising edge of
5$6
and
&$6 between t
OHR and tOH and between tOFR and tOFF.
22. t
DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6 s after either burst refresh or distributed refresh at
equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6s after exiting from self refresh mode.
24. In case of entering from
5$6-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
25. For L-version, it is available to apply each 128 ms and 31.2 s instead of 64 ms and 15.6 s at
note 23.
26 At t
RASS > 100 s, self refresh mode is activated, and not activated at tRASS < 10 s.
It is
undefined within the range of 10 s
≤ t
RASS ≤ 100 s.
For t
RASS ≥ 10 s, it is necessary to satisfy
t
RPS.
27. XXX: H or L (H: V
IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH or VIL.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HM51680J | 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL |
| HM51-680J | 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL |
| HM51-680JLF | 制造商:BITECH 制造商全称:Bi technologies 功能描述:Axially Leaded Miniature Power Inductors |
| HM51680K | 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL |
| HM51-680K | 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL |
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