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参数资料
| 型号： | HMC742HFLP5E |
| 厂商： | HITTITE MICROWAVE CORP |
| 元件分类： | 放大器 |
| 英文描述： | 500 MHz - 4000 MHz RF/MICROWAVE WIDE BAND MEDIUM POWER AMPLIFIER |
| 封装： | 5 X 5 MM, ROHS COMPLIANT, LEADLESS, PLASTIC, SMT, QFN-32 |
| 文件页数： | 5/10页 |
| 文件大小： | 740K |
| 代理商： | HMC742HFLP5E |
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For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
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HMC742HFLP5E
v00.0211
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL
VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz
Serial Control Interface
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
The HMC742HFLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). The serial control interrface
is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK
and LE requires clean transitions. If mechanical switches are used, sufficient debouncing should be provided. When
LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to
prevent data transition during output loading.
When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and the input register is loaded with
parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data changes the state of the part per truth table.
For all modes of operations, the DVGA state will stay constant while LE is kept low.
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch
Enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the LE is pulsed. See timing diagram above for reference.
Timing Diagram (Latched Parallel Mode)
Parameter
Typ.
Min. serial period, t
SCK
100 ns
Control set-up time, t
CS
20 ns
Control hold-time, t
CH
20 ns
LE setup-time, t
LN
10 ns
Min. LE pulse width, t
LEW
10 ns
Min LE pulse spacing, t
LES
630 ns
Serial clock hold-time from LE, t
CKN
10 ns
Hold Time, t
PH.
0 ns
Latch Enable Minimum Width, t
LEN
10 ns
Setup Time, t
PS
2 ns
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