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参数资料
| 型号： | HMC742HFLP5E |
| 厂商： | HITTITE MICROWAVE CORP |
| 元件分类： | 放大器 |
| 英文描述： | 500 MHz - 4000 MHz RF/MICROWAVE WIDE BAND MEDIUM POWER AMPLIFIER |
| 封装： | 5 X 5 MM, ROHS COMPLIANT, LEADLESS, PLASTIC, SMT, QFN-32 |
| 文件页数： | 6/10页 |
| 文件大小： | 740K |
| 代理商： | HMC742HFLP5E |
12 - 5
For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
V
A
R
IA
B
LE
G
A
IN
A
M
P
LI
F
IE
R
S
-
D
IG
IT
A
L-
S
M
T
12
Absolute Maximum Ratings
RF Input Power at Max Gain [1]
17.5 dBm (T = +85 °C)
Digital Inputs (LE, SERIN, CLK, P/S,
DO-D5, PUP1, PUP2)
-0.5 to Vdd +0.5V
Controller Bias Voltage (Vdd)
5.6V
Amplifier Bias Voltage (Vcc)
5.5V
Channel Temperature
175 °C
Continuous Pdiss (T = 85 °C)
(derate 13.3 mW/°C above 85 °C) [2]
1.2 W
Thermal Resistance [3]
75.6 °C/W
Storage Temperature
-65 to +150 °C
Operating Temperature
-40 to +85 °C
ESD Sensitivity (HBM)
Class 1A
[1] The maximum RF input power increases by the same amount
the gain is reduced. The maximum input power at any state is no
more than 28 dBm.
[2] This value does not include the RF power dissipation in the
attenuator. The loss in the attenuator depends on the state of
the attenuator. The loss in the attenuator should be included to
determine the total power dissipation in the part.
[3] This value does not include the RF power dissipation in the
attenuator. The thermal resistance at different states of the
attenuator can be determined based on note [2]
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Bias Voltage
PUP Truth Table
LE
PUP1
PUP2
Gain Relative to Maximum
Gain
0
-31.5
0
1
0
-24
0
1
-16
0
1
Insertion Loss
1
X
0 to -31.5 dB
Note: The logic state of D0 - D5 determines the
power-up state per truth table shown below when LE
is high at power-up.
Power-Up States
Vdd (V)
Idd (Typ.) (mA)
+5.0
0.12
Vs (V)
Is (mA)
+5.0
150
Control Voltage Input
Gain
Relative to
Maximum
Gain
D5
D4
D3
D2
D1
D0
High
0 dB
High
Low
-0.5 dB
High
Low
High
-1 dB
High
Low
High
-2 dB
High
Low
High
-4 dB
High
Low
High
-8 dB
Low
High
-16 dB
Low
-31.5 dB
Any combination of the above states will provide a reduction in
gain approximately equal to the sum of the bits selected.
Truth Table
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines the
power-up state of the part per truth table. The DVGA
latches in the desired power-up state approximately
200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
HMC742HFLP5E
v00.0211
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL
VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz
Control Voltage Table
State
Vdd = +3V
Vdd = +5V
Low
0 to 0.5V @ <1 A
0 to 0.8V @ <1 A
High
2 to 3V @ <1 A
2 to 5V @ <1 A
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