- 您现在的位置：买卖IC网 > PDF目录370643 > HMS30C7202N (Electronic Theatre Controls, Inc.) Highly-intergrated MPU PDF资料下载
参数资料
| 型号： | HMS30C7202N |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微处理器 |
| 文件页数： | 7/179页 |
| 文件大小： | 2127K |
| 代理商： | HMS30C7202N |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页
HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 2 -
5.4.1
5.4.2
5.4.3
Reset Sequences of Power On Reset........................................................................................................... 34
Software Generated Warm Reset................................................................................................................ 35
An Externally generated Warm Reset......................................................................................................... 35
6
SDRAM CONTROLLER........................................................................................................................................ 37
6.1
6.2
S
UPPORTED
M
EMORY
D
EVICES
............................................................................................................................ 37
R
EGISTERS
.......................................................................................................................................................... 38
6.2.1
SDRAM Controller Configuration Register (SDCON)............................................................................... 38
6.2.2
SDRAM Controller Refresh Timer Register (SDREF)................................................................................ 40
6.2.3
SDRAM Controller Write buffer flush timer Register (SDWBF)................................................................. 40
6.2.4
SDRAM Controller Wait Driver Register (SDWAIT).................................................................................. 40
6.3
P
OWER
-
UP
I
NITIALIZATION OF THE
SDRAM
S
....................................................................................................... 40
6.4
SDRAM
M
EMORY
M
AP
...................................................................................................................................... 41
6.5
AMBA
A
CCESSES AND
A
RBITRATION
.................................................................................................................. 42
6.6
M
ERGING
W
RITE
B
UFFER
.................................................................................................................................... 42
7
STATIC MEMORY INTERFACE.......................................................................................................................... 44
7.1
7.2
E
XTERNAL
S
IGNALS
............................................................................................................................................. 44
F
UNCTIONAL
D
ESCRIPTION
.................................................................................................................................. 44
7.2.1
Memory bank select.................................................................................................................................... 44
7.2.2
Access sequencing...................................................................................................................................... 44
7.2.3
Wait states generation ................................................................................................................................ 45
7.2.4
Burst read control....................................................................................................................................... 45
7.2.5
Byte lane write control ............................................................................................................................... 45
7.3
R
EGISTERS
.......................................................................................................................................................... 46
7.3.1
MEM Configuration Register..................................................................................................................... 46
7.4
E
XAMPLES OF THE
SMI
R
EAD
,
W
RITE WAIT TIMING DIAGRAM
.............................................................................. 47
7.4.1
Read normal wait (Non-Sequential mode).................................................................................................. 47
7.4.2
Read normal wait (Sequential mode) ......................................................................................................... 48
7.4.3
Read burst wait (Sequential mode)............................................................................................................. 49
7.4.4
Write normal wait (Sequential mode)......................................................................................................... 50
7.5
I
NTERNAL
SRAM................................................................................................................................................ 51
7.5.1
Remapping Enable Register....................................................................................................................... 51
7.5.2
Remap Source Address Register................................................................................................................. 51
8
LCD CONTROLLER.............................................................................................................................................. 52
8.1
V
IDEO OPERATION
............................................................................................................................................... 52
8.1.1
LCD datapath............................................................................................................................................. 53
8.1.1.1
Palette RAM & 16bpp mode.................................................................................................................. 53
8.1.2
Color/Grayscale Dithering......................................................................................................................... 55
8.1.3
How to order the bit on LD[7:0] output..................................................................................................... 55
8.1.4
TFT mode................................................................................................................................................... 56
8.2
R
EGISTERS
.......................................................................................................................................................... 56
8.2.1
LCD Power Control ................................................................................................................................... 56
8.2.2
LCD Controller Status/Mask and Interrupt Registers ................................................................................ 57
8.2.3
LCD DMA Base Address Register.............................................................................................................. 58
8.2.4
LCD DMA Channel Current Address Register........................................................................................... 58
8.2.5
LCD Timing 0 Register............................................................................................................................... 58
8.2.6
LCD Timing 1 Register............................................................................................................................... 59
8.2.7
LCD Timing 2 Register............................................................................................................................... 60
8.2.8
LCD Test Register....................................................................................................................................... 61
8.2.9
Grayscaler Test Registers........................................................................................................................... 61
8.2.10
LCD Palette registers................................................................................................................................. 62
8.3
T
IMINGS
.............................................................................................................................................................. 63
9
FAST AMBA PERIPHERALS................................................................................................................................ 64
9.1
DMA
C
ONTROLLER
............................................................................................................................................. 64
9.1.1
External Signals......................................................................................................................................... 64
9.1.2
Registers..................................................................................................................................................... 64
9.1.2.1
ADR0..................................................................................................................................................... 65
相关PDF资料 |
PDF描述 |
|---|---|
| HMS81C2012A | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AK | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012ALQ | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AQ | INDUCTOR*100UH*0.73AMP*0.672OHM*15%*SURFACE MOUNT |
| HMS81C2020A | INDCTR, PWR, SMT 1.5UH, 15%, 6.9 A |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HMS30C7210 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ARM Based 32-Bit Microprocessor |
| HMS3224M3 | 制造商:HANBIT 制造商全称:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-10 | 制造商:HANBIT 制造商全称:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-12 | 制造商:HANBIT 制造商全称:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-15 | 制造商:HANBIT 制造商全称:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
发布紧急采购，3分钟左右您将得到回复。