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参数资料
型号： HW-V5-ML561-UNI-G-J
厂商： Xilinx Inc
文件页数： 10/91页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-5
产品变化通告： Development Systems Discontinuation 16/Jan/2012
标准包装： 1
系列： Virtex®-5 LXT
类型： FPGA
适用于相关产品： XC5VLX50T-FFG1136
所含物品： 评估平台，线缆，CD，小型闪存卡，DDR2 DIMM，- 不包括电源 -
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
18
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max
Units
FGTPRX
Serial data rate
RX oversampler not enabled
0.5
FGTPMAX
Gb/s
RX oversampler enabled
0.1
0.5
Gb/s
RXOOBVDPP
OOB detect threshold
peak-to-peak
OOBDETECT_THRESHOLD = 100
60
105
165
mV
RXSST
Receiver spread-spectrum
tracking(1)
Modulated @ 33 KHz
–5000
0
ppm
RXRL
Run length (CID)
Internal AC capacitor bypassed
150
UI
RXPPMTOL
Data/REFCLK PPM offset
tolerance(2)
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 1(3)
–200
200
ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 2(3)
–200
200
ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 4(3)
–100
100
ppm
CDR 2nd-order loop enabled
–1000
1000
ppm
SJ Jitter Tolerance(4)
JT_SJ3.75
Sinusoidal Jitter(5)
3.75 Gb/s
0.30
UI
JT_SJ3.2
Sinusoidal Jitter(5)
3.20 Gb/s
0.40
UI
JT_SJ2.50
Sinusoidal Jitter(5)
2.50 Gb/s
0.40
UI
JT_SJ2.00
Sinusoidal Jitter(5)
2.00 Gb/s
0.40
UI
JT_SJ1.00
Sinusoidal Jitter(5)
1.00 Gb/s
0.30
UI
JT_SJ500
Sinusoidal Jitter(5)
500 Mb/s
0.30
UI
JT_SJ500
Sinusoidal Jitter(5)
500 Mb/s OS
0.30
UI
JT_SJ100
Sinusoidal Jitter(5)
100 Mb/s OS
0.30
UI
SJ Jitter Tolerance with Stressed Eye(4)
JT_TJSE3.2
Total Jitter with Stressed
Eye(6)
3.20 Gb/s
0.87
UI
JT_SJSE3.2
Sinusoidal Jitter with
Stressed Eye(6)
3.20 Gb/s
0.30
UI
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1 only.
2.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3.
CDR 1st-order step size set to 2.
4.
All jitter values are based on a Bit Error Ratio of 1e–12.
5.
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
6.
Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
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