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参数资料
| 型号： | HX6356KVRT |
| 元件分类： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 25 ns, UUC |
| 封装： | DIE |
| 文件页数： | 5/12页 |
| 文件大小： | 145K |
| 代理商： | HX6356KVRT |
HX6356
2
SIGNAL DEFINITIONS
A: 0-14
Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
NCS
CE
NWE
NOE
MODE
DQ
L
H
L
Read
Data Out
L
H
L
X
Write
Data In
H
X
XX
Deselected
High Z
X
L
XX
Disabled
High Z
TRUTH TABLE
FUNCTIONAL DIAGRAM
Notes:
X: VI=VIH or VIL
XX: VSS
≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
NCS
A:0-8,12-13
CE
NWE
NOE
WE CS CE
NWE CS CE OE
Column Decoder
Data Input/Output
Row
Decoder
32,768 x 8
Memory
Array
A:9-11, 14
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
4
DQ:0-7
(0 = high Z)
8
11
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