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参数资料
| 型号： | HY29LV320TF-90 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| 中文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA63 |
| 封装： | 7 X 11 MM, FBGA-63 |
| 文件页数： | 19/44页 |
| 文件大小： | 323K |
| 代理商： | HY29LV320TF-90 |
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19
r1.3/May 02
HY29LV320
Chip Erase Command Sequence
The Chip Erase Command sequence consists of
two unlock cycles, followed by a set-up command,
two additional unlock cycles and then the Chip
Erase Command. This sequence invokes the
Automatic Chip Erase algorithm which automati-
cally preprograms (if necessary) and verifies the
entire memory for an all zero data pattern before
electrical erase. The host system is not required
to provide any controls or timings during these
operations.
If all sectors in the device are protected, the de-
vice returns to reading array data after approxi-
mately 100 μs. If at least one sector is unpro-
tected, the erase operation erases the unprotected
sectors, and ignores the command for the sectors
that are protected. Reads from the device during
operation of the Automatic Chip Erase Algorithm
return status data. See Write Operation Status
section of this specification.
Commands written to the device during execution
of the Automatic Chip Erase algorithm are ignored.
Note that a hardware reset immediately terminates
the chip erase operation (see Hardware Reset Tim-
ings). To ensure data integrity, the user should
reinitiate the aborted Chip Erase Command se-
quence after the reset operation is complete.
When the Automatic Chip Erase algorithm is com-
plete, the device returns to the reading array data
mode. Several methods are provided to allow the
host to determine the status of the erase opera-
tion, as described in the Write Operation Status
section.
Figure 7 illustrates the chip erase procedure.
Sector Erase Command Sequence
The Sector Erase Command sequence consists
of two unlock cycles, followed by a set-up com-
mand, two additional unlock cycles and then the
Sector Erase Command, which specifies which
sector is to be erased. This sequence invokes
the Automatic Sector Erase algorithm which auto-
matically preprograms (if necessary) and verifies
the specified sector for an all zero data pattern
before electrical erase. The host system is not
required to provide any controls or timings during
these operations.
After the sector erase command cycle (sixth cycle)
of the command sequence is issued, a sector
erase time-out of 50 μs (min) begins, measured
from the rising edge of the final WE# pulse in the
command sequence. During this time, an addi-
tional sector address and Sector Erase Command
may be written into an internal sector erase buffer.
This buffer may be loaded in any sequence, and
the number of sectors designated for erasure may
be from one sector to all sectors. The only re-
striction is that the time between these additional
cycles must be less than 50 μs, otherwise era-
sure may begin before the last address and com-
mand are accepted. To ensure that all commands
are accepted, it is recommended that host pro-
cessor interrupts be disabled during the time that
the additional sector erase commands are being
issued and then be re-enabled afterwards.
The system can monitor DQ[3] to determine if the
50 μs sector erase time-out has expired, as de-
scribed in the Write Operation Status section. If
the time between additional sector erase com-
mands can be assured to be less than the time-
out, the system need not monitor the timeout.
Note:
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to
reading array data. The system must then rewrite the
command sequence, including any additional sector
addresses and commands. Once the sector erase op-
eration itself has begun, only the Erase Suspend com-
mand is valid. All other commands are ignored.
As for the chip erase command, note that a hard-
ware reset immediately terminates the erase op-
eration (see Hardware Reset Timings). To ensure
data integrity, the aborted sector erase command
sequence should be reissued once the reset op-
eration is complete.
START
Issue CHIP ERASE
Command Sequence
Check Erase Status
(See Write Operation Status
Section)
CHIP ERASE COMPLETE
GO TO
ERROR RECOVERY
DQ[5] Error Exit
Normal Exit
Figure 7. Chip Erase Procedure
相关PDF资料 |
PDF描述 |
|---|---|
| HY29LV320BF-12 | Dust Cover; For Use With:Anderson Power SB350 Series Connectors; Color:Red |
| HY29LV320BF-12I | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TT-90 | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320BT-90 | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TF-70 | 32 Mbit (2M x 16) Low Voltage Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY29LV320TF-90I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TT-12 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TT-12I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TT-70 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TT-70I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
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