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参数资料
| 型号： | HY5PS1G831CLFP-C4 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM |
| 中文描述： | 128M X 8 DDR DRAM, 0.5 ns, PBGA60 |
| 封装： | ROHS COMPLIANT, FBGA-60 |
| 文件页数： | 32/37页 |
| 文件大小： | 539K |
| 代理商： | HY5PS1G831CLFP-C4 |
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Rev. 0.2 / Dec 2006
32
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
9. tIS and tIH (input setup and hold) derating
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the
datasheet value to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
(dc) and the first crossing of V
(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of V
(dc) and the first crossing of V
(ac)max. If the actual signal is
always earlier than the nominal slew rate for line between shaded ‘V
REF
(dc) to ac region’, use nominal slew
rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘V
(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level
to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of V
REF
(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of V
(dc). If the actual
σιγναλ
is always later than the nominal slew
rate line between shaded ‘dc to V
(dc) region’, use nominal slew rate for derating value(see Fig.c) If the
actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V
REF
(dc) region’, the
slew rate of a tangent line to the actual signal from the dc level to V
REF
(dc) level is used for derating
value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached
V
(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transi-
tion and reach V
IH/IL
(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
△
tIS
△
tIH
△
tIS
△
tIH
△
tIS
△
tIH
Units
Notes
4.0
+187
+94
TBD
TBD
TBD
TBD
ps
1
3.5
+179
+89
TBD
TBD
TBD
TBD
ps
1
3.0
+167
+83
TBD
TBD
TBD
TBD
ps
1
2.5
+150
+75
TBD
TBD
TBD
TBD
ps
1
2.0
+125
+45
TBD
TBD
TBD
TBD
ps
1
1.5
+83
+21
TBD
TBD
TBD
TBD
ps
1
1.0
+0
0
TBD
TBD
TBD
TBD
ps
1
0.9
-11
-14
TBD
TBD
TBD
TBD
ps
1
0.8
-25
-31
TBD
TBD
TBD
TBD
ps
1
0.7
-43
-54
TBD
TBD
TBD
TBD
ps
1
0.6
-67
-83
TBD
TBD
TBD
TBD
ps
1
0.5
-100
-125
TBD
TBD
TBD
TBD
ps
1
0.4
-150
-188
TBD
TBD
TBD
TBD
ps
1
0.3
-223
-292
TBD
TBD
TBD
TBD
ps
1
0.25
-250
-375
TBD
TBD
TBD
TBD
ps
1
0.2
-500
-500
TBD
TBD
TBD
TBD
ps
1
0.15
-750
-708
TBD
TBD
TBD
TBD
ps
1
0.1
-1250
-1125
TBD
TBD
TBD
TBD
ps
1
tIS, tIH Derating Values
Differential Slew Rate
Command /
Address
Slew
rate(V/ns)
2.0 V/ns
CK, CK
1.5 V/ns
1.0 V/ns
相关PDF资料 |
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|---|---|
| HY5PS1G831CLFP-E3 | 1Gb DDR2 SDRAM |
| HY5PS1G831CLFP-S5 | 1Gb DDR2 SDRAM |
| HY5PS1G831CLFP-Y5 | 1Gb DDR2 SDRAM |
| HY5PS1G821LM-E3 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821M | 1Gb DDR2 SDRAM(DDP) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G831CLFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CLFP-S5 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CLFP-Y5 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831F | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831F-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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