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参数资料
| 型号： | HY5RS573225AFP-16L |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.28 ns, PBGA136 |
| 封装： | 11 X 14 MM, ROHS COMPLIANT, FBGA-136 |
| 文件页数： | 24/64页 |
| 文件大小： | 1096K |
| 代理商： | HY5RS573225AFP-16L |
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HY5RS573225AFP
Rev. 1.7 / Aug. 2006
30
WRITE Timing
WRITE burst is initiated with a WRITE command.
The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled
or disabled for that burst access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged
at the completion of the burst after tRAS minimum has been met.
During WRITE bursts, the first valid data-in element will be registered on the rising edge of WDQS following the write
latency set in the mode register and subsequent data elements will be registered on successive edges of WDQS. Prior
to the first valid WDQS rising edge, a cycle is needed and specified as the WRITE Preamble. The preamble consists of
a half cycle High followed by a half cycle Low driven by the controller. The cycle on WDQS following the last data-in
element is known as the write postamble and must be driven High by the controller, it can not be left to float High
using the on die termination. The WDQS should only toggle on data transfers.
The time between the WRITE command and the first valid rising edge of WDQS (tDQSS) is specified relative to the
write latency (WL - 0.25CK and WL + 0.25CK). All of the WRITE diagrams show the nominal case, and where the two
extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon com-
pletion of a burst, assuming no other command has been initiated, the DQs should remain Hi-Z and any additional
input data will be ignored.
Data for any WRITE burst may not be truncated with any subsequent command.
A subsequent WRITE command can be issued on any positive edge of clock following the previous WRITE command
assuming the previous burst has completed. The subsequent WRITE command can be issued x cycles after the previ-
ous WRITE command, where x equals the number of desired nibbles x2 (nibbles are required by 4n-prefetch architec-
ture) i.e. BL/2. A subsequent READ command can be issued once tWTR is met or a subsequent PRECHARGE command
can be issued once tWR is met. After the PRECHARGE command, a subsequent command to the same bank cannot be
issued until tRP is met.
CA
BA
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
A0~A7, A9
A10, A11
A8
BA0, 1
HIGH
EN AP
DIS AP
CA= Column Address
BA= Bank Address
EN AP= Enable Auto Precharge
DIS AP= Disable Auto Precharge
DON'T CARE
Figure 19
WRITE Command
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相关代理商/技术参数 |
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|---|---|
| HY5S2B6DLF-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-SE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLF-SE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S5B2BLF-6E | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM |
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