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| 型号： | HY5RS573225AFP-16L |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.28 ns, PBGA136 |
| 封装： | 11 X 14 MM, ROHS COMPLIANT, FBGA-136 |
| 文件页数： | 37/64页 |
| 文件大小： | 1096K |
| 代理商： | HY5RS573225AFP-16L |
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HY5RS573225AFP
Rev. 1.7 / Aug. 2006
42
NOTE (continued):
3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two
parts; the access period and the precharge period. For read with auto precharge, the precharge period is defined
as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRE
CHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge
period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts
with registration of the command and ends where the precharge period (or tRP) begins.
During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states,
ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other
related limitations apply (e.g., contention between read data and write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different
is summarized below.
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
7. Requires appropriate DM masking.
TABLE 5 : Minimum Delay Between Commands to Different Banks
with Auto Precharge Enabled
NOTE :
CL = CAS Latency (CL) rounded up to the next integer.
BL = Burst Length
WL = WRITE Latency
1) Write Data cannot be driven onto the DQ bus for 2 clocks after the READ Data is off the bus.
(Refer to Figure 17 on the page28)
From
Command
To Command
Minimum delay (with concurrent auto precharge)
WRITE w/AP
READ or READ w/AP
[WL+(BL/2)] tCK+tWTR
WRITE or WRITE w/AP
(BL/2) tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ w/AP
READ or READ w/AP
(BL/2)*tCK
WRITE or WRITE w/AP
[CL+(BL/2)+2-WL] tCK1)
PRECHARGE
1 tCK
ACTIVE
1 tCK
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