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参数资料
| 型号： | HY5RS573225AFP-16L |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.28 ns, PBGA136 |
| 封装： | 11 X 14 MM, ROHS COMPLIANT, FBGA-136 |
| 文件页数： | 8/64页 |
| 文件大小： | 1096K |
| 代理商： | HY5RS573225AFP-16L |
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HY5RS573225AFP
Rev. 1.7 / Aug. 2006
16
NOTE:
1. E13 and E12(BA0 and BA1) must be “1,0” to select the Extended Mode Register (vs. the base Mode Register).
2. RFU: Reserved for future use.
3. The ODT Disable Function disables DQ, WDQS, RDQS & DM pins.
4. The default setting at Power Up for A3, A2 is 10 or 11
5. A9, A8 may be used optionally for Low Power mode, Additive Latency setting respectively. And Hynix GDDR3
has the Additive Latency implemented, but not the Low Power mode.
6. If the user activates bits in the extended mode register in an optional field, either the optional feature is activated
(if option implemented in the device) or no action is taken by the device (if option not implemented).
7. The Drive Strength (A1, A0) values of 35, 40 and 45 omhs are only intended as targets under typical conditions.
In addition when any of these values are selected the termination values may scale with the selected impedence.
8. WR (write recovery time for autoprecharge) in clock cycles is calculated by dividing tWR (in ns) by tCK(in ns) and
rounding up to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this
value.
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| HY5S2B6DLF-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
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