参数资料
型号: HYMD18M645AL6-K
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 8M X 64 DDR DRAM MODULE, 0.75 ns, DMA200
封装: 67.60 X 31.75 X 1 MM, SODIMM-200
文件页数: 1/16页
文件大小: 232K
代理商: HYMD18M645AL6-K
8Mx64 bits
Unbuffered DDR SDRAM SO-DIMM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5/May. 02
1
HYMD18M645A(L)6-K/H/L
DESCRIPTION
Hynix HYMD18M645A(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual
In-Line Memory Modules (SO-DIMMs) which are organized as 8Mx64 high-speed memory arrays. Hynix
HYMD18M645A(L)6-K/H/L series consists of four 8Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-
epoxy substrate. Hynix HYMD18M645A(L)6-K/H/L series provide a high performance 8-byte interface in 67.60mmX
31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD18M645A(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-
ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD18M645A(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Factor
HYMD18M645A(L)6-K
VDD=2.5V
VDDQ=2.5V
133MHz(*DDR266A)
SSTL_2
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
HYMD18M645A(L)6-H
133MHz (*DDR266B)
HYMD18M645A(L)6-L
100MHz (*DDR200)
64MB (8M x 64) Unbuffered DDR SO-DIMM based on
8Mx16 DDR SDRAM
JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
* JEDEC Defined Specifications compliant
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相关代理商/技术参数
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