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参数资料
| 型号： | HYMD18M645AL6-K |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封装： | 67.60 X 31.75 X 1 MM, SODIMM-200 |
| 文件页数： | 7/16页 |
| 文件大小： | 232K |
| 代理商： | HYMD18M645AL6-K |
HYMD18M645A(L)6-K/H/L
Rev. 0.5/May. 02
15
SERIAL PRESENCE DETECT
Byte#
Function Description
Function Supported
Hexa Value
Note
K
H
L
K
H
L
0
Number of Bytes written into serial memory at module
manufacturer
128 Bytes
80h
1
Total number of Bytes in SPD device
256 Bytes
08h
2
Fundamental memory type
DDR SDRAM
07h
3
Number of row address on this assembly
12
0Ch
1
4
Number of column address on this assembly
9
09h
1
5
Number of physical banks on DIMM
1Bank
01h
6
Module data width
64 Bits
40h
7
Module data width (continued)
-
00h
8
Module voltage Interface levels(VDDQ)
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
7.5ns
8ns
75h
80h
2
10
DDR SDRAM access time from clock at CL=2.5 (tAC)
+/-0.75ns +/-0.75ns
+/-0.8ns
75h
80h
2
11
Module configuration type
Non-ECC
00h
12
Refresh rate and type
15.6us & Self refresh
80h
13
Primary DDR SDRAM width
x16
10h
14
Error checking DDR SDRAM data width
N/A
00h
15
Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
01h
16
Burst lengths supported
2,4,8
0Eh
17
Number of banks on each DDR SDRAM
4 Banks
04h
18
CAS latency supported
2, 2.5
0Ch
19
CS latency
0
01h
20
WE latency
1
02h
21
DDR SDRAM module attributes
differential clock input
20h
22
DDR SDRAM device attributes : General
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
40h
23
DDR SDRAM cycle time at CL=2.0(tCK)
7.5ns
10ns
75h
A0h
24
DDR SDRAM access time from clock at CL=2.0(tAC)
+/-0.75ns +/-0.75ns
+/-0.8ns
75h
80h
25
DDR SDRAM cycle time at CL=1.5(tCK)
-
00h
26
DDR SDRAM access time from clock at CL=1.5(tAC)
-
00h
27
Minimum row precharge time(tRP)
20ns
50h
28
Minimum row activate to row active delay(tRRD)
15ns
3Ch
29
Minimum RAS to CAS delay(tRCD)
20ns
50h
30
Minimum active to precharge time(tRAS)
45ns
50ns
2Dh
32h
31
Module row density
64MB
10h
32
Command and address signal input setup time(tIS)
0.9ns
1.1ns
90h
B0h
33
Command and address signal input hold time(tIH)
0.9ns
1.1ns
90h
B0h
34
Data signal input setup time(tDS)
0.5ns
0.6ns
50h
60h
35
Data signal input hold time(tDH)
0.5ns
0.6ns
50h
60h
36~40 Reserved for VCSDRAM
Undefined
00h
41
Minimum active / auto-refresh Time (tRC)
65ns
70ns
41h
46h
42
Minimum auto-refresh to active / auto-refresh
command period (tRFC)
75ns
80ns
4Bh
50h
43
Maximum cycle time (tCK max)
12ns
30h
44
Maximum DQS-DQ skew time (tDQSQ)
0.5ns
0.6ns
32h
3Ch
45
Maximum read data hold skew factor (tQHS)
0.75ns
75h
46~61 Superset Information(may be used in future)
Undefined
00h
62
SPD Revision code
Initial release
00h
63
Checksum for Bytes 0~62
-
0Bh
36h
D0h
Bin Sort
: K(DDR266A@CL=2), H(DDR266B@CL=2.5), L(DDR200@CL=2)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYMD18M645AL6-L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|DDR|8MX64|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8Mx72|2.5V|K/H/L|x5|DDR SDRAM - SO DIMM 64MB |
| HYMD18M725A6-H | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6-K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6-L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
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