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| 型号： | IBM0117405M |
| 厂商： | IBM Microeletronics |
| 英文描述： | 4M x 4 11/11 EDO DRAM(16M位 动态RAM（超页面模式读写并带22条地址线，其中11条为行地址选通，11条为列地址选通）) |
| 中文描述： | 4米× 4 11/11 EDO公司的DRAM（1,600位动态随机存储器（超页面模式读写并带22条地址线，其中11条为行地址选通，11条为列地址选通）） |
| 文件页数： | 30/31页 |
| 文件大小： | 545K |
| 代理商： | IBM0117405M |
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IBM0117405
IBM0117405B
4M x 4 11/11 EDO DRAM
IBM0117405M
IBM0117405P
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 30 of 31
28H4726
SA14-4228-05
Revised 4/97
Revision Log
Revision
Contents Of Modification
11/15/95
Initial Release
12/10/95
1. The Low Power and Standard Power Specifications were combined. ES# 28H4725 and ES# 28H4726 were
combined into ES# 28H4726.
2. Added Die Rev E part numbers.
3. t
CHD
was added to the Self Refresh Cycle with a value of 350
μ
s for all speed sorts.
4. The Self Refresh timing diagram was changed to allow CAS to go high t
CHD
(350
μ
s) after RAS falls entering a
Self Refresh.
5. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
6. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “L” to ” H”.
09/01/96
1. I
CC1
, I
CC3
, and I
CC6
were changed from 95mA to 105mA for the -50 speed sort.
2. I
CC2
was changed from 2mA to 1mA.
3. I
I(L)
and I
O(L)
were altered from +/- 10uA to +/- 5uA.
4. t
RC
was changed from 89ns to 84ns for the -50 speed sort.
5. t
CSH
changed from 45ns to 38ns, 50ns to 45ns, and 55ns to 50ns for the -50, -60, and -70 speed sorts, respec-
tively.
6. t
T
was initially at a max of 30ns. It has been modified to 50ns for all speed sorts.
7. t
CPA
was decreased from 30ns to 28ns for the -50 speed sort.
8. t
RASP
max of 125K was raised to 200K for all speed sorts.
9. t
OEP
was changed from 10ns to 5ns for all speed sorts.
10. t
OEHC
was also lowered from 10ns to 5ns for all speed sorts.
11. t
RP
was changed from 35ns to 30ns for the -50 speed sort.
03/19/97
1. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “H” to “L
→
H”.
2. t
OED
was moved from the Common Parameters table to the Write Cycle Parameters Table.
3. t
RWC
for the -50 part was changed from 115ns to 100ns.
4. The note “Implementing WE at RAS time during a Read or Write cycle is optional. Doing so will facilitate com-
patibility with future EDO DRAMs.” was removed from all of the Read and Write timing diagrams.
5. t
ODD
in the CAS before RAS timing diagram was renamed t
OED
.
6. The -70 speed sort and timings were removed.
7. I
cc1
, I
cc3
, I
cc6
for the -50 speed sort were reduced from 105mA to 75mA.
8. I
cc4
for the -50 speed sort was reduced from 75mA to 35mA.
9. I
cc1
, I
cc3
, I
cc6
for the -60 speed sort were reduced from 85mA to 60mA.
10. I
cc4
for the -60 speed sort was reduced from 65mA to 30mA.
04/23/97
1. I
cc5
was changed from 200
μ
A to 100
μ
A for the Low Power Die Rev F Parts.
Discontinued (9/98 - last order; 3/99 last ship)
相关PDF资料 |
PDF描述 |
|---|---|
| IBM0117405P | 4M x 4 11/11 EDO DRAM(16M位 动态RAM（超页面模式读写并带22条地址线，其中11条为行地址选通，11条为列地址选通）) |
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| IBM0117805B | 2M x 8 11/10 EDO DRAM(16M位 动态RAM（超页面模式读写并带21条地址线，其中11条为行地址选通，10条为列地址选通）) |
| IBM0117805M | 2M x 8 11/10 EDO DRAM(16M位 动态RAM（超页面模式读写并带21条地址线，其中11条为行地址选通，10条为列地址选通）) |
| IBM0117805P | 2M x 8 11/10 EDO DRAM(16M位 动态RAM（超页面模式读写并带21条地址线，其中11条为行地址选通，10条为列地址选通）) |
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