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参数资料
| 型号： | IBM25EMPPC740LDBA3330 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 27/50页 |
| 文件大小： | 600K |
| 代理商： | IBM25EMPPC740LDBA3330 |
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5/20/99
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
Page 29
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
Pinout Listing for the 360 CBGA package
Signal Name
Pin Number
Active
I/O
A0-A31
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2,
L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2
High
I/O
AACK
N3
Low
Input
ABB
L7
Low
I/O
AP0-AP3
C4, C5, C6, C7
High
I/O
ARTRY
L6
Low
I/O
AVDD
A8
——
BG
H1
Low
Input
BR
E7
Low
Output
BVSEL
W016
—
Input
CKSTP_OUT
D7
Low
Output
CI
C2
Low
Output
CKSTP_IN
B8
Low
Input
CLKOUT
E3
--
Output
DBB
K5
Low
I/O
DBDIS
G1
Low
Input
DBG
K1
Low
Input
DBWO
D1
Low
Input
DH0-DH31
W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10,
W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3,
U4, R5
High
I/O
DL0-DL31
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13,
W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3,
U3, W2
High
I/O
DP0-DP7
L1, P2, M2, V2, M1, N2, T3, R1
High
I/O
DRTRY
H6
Low
Input
GBL
B1
Low
I/O
GND
D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11,
H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16,
L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16,
R8, R12, T4, T6, T10, T14, T16
——
Note:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
3. Internally tied to L2OVDD in the 750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. L2_TSTCLK may be tied to ground for normal machine operation, if extra 60x bus output hold is required on all 60x bus signals. See Table “60X Bus
6. These pins are no connects on dd2.x and have no function. They will be added to dd3.x to select voltage levels for the L2 bus (A19) and the rest of the
I/O (W01). Leaving the pin unconnected will select the normal supply value. Connecting these pins to HRESET# or ground on dd3.x will select lower
voltage supply ranges.
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