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参数资料
| 型号： | IBM25EMPPC740LDBA3330 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 35/50页 |
| 文件大小： | 600K |
| 代理商： | IBM25EMPPC740LDBA3330 |
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Page 36
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
PLL Power Supply Filtering
The AV
DD and L2AVDD power signals are provided on the 750 to provide power to the clock generation phase-
locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power
supplied to the AV
DD input signal should be filtered using a circuit similar to the one shown in Figure 18. The
circuit should be placed as close as possible to the AV
DD pin to ensure it filters out as much noise as possible.
An identical but separate circuit should be placed as close as possible to the L2AV
DD pin.
Decoupling Recommendations
Due to the dynamic power management of the 750, which features large address and data buses, as well as
high operating frequencies, the 750 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the 750750 system, and the 750 itself requires a clean, tightly regulated source of
power. Therefore, it is strongly recommended that the system designer place at least one decoupling capaci-
tor with a low ESR (effective series resistance) rating at each V
DD and OVDD pin (and L2OVDD for the 360
CBGA) of the 750. It is also recommended that these decoupling capacitors receive their power from sepa-
rate V
DD, OVDD and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should range in value from 220pF to 10
F to provide both high and low- frequency filtering,
and should be placed as close as possible to their associated V
DD or OVDD pins. Suggested values for the VDD
pins – 220pF (ceramic), 0.01
F (ceramic), and 0.1f (ceramic). Suggested values for the OV
DD pins – 0.01
F
(ceramic), 0.1
f (ceramic), and 10F (tantalum). Only SMT (surface-mount technology) capacitors should be
used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-
ing the V
DD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100
F (AVX TPS tantalum) or 330F (AVX TPS tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to V
DD. Unused active high inputs should be connected to GND.
All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD, OVDD, and GND, pins of the 750.
Figure 18. PLL Power Supply Filter Circuit
VDD
AV
DD (or L2AVDD)
10
10
F
0.1
F
GND
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| IBM25EMPPC740LEBA300 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-Bit Microprocessor |
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| IBM25EMPPC740LEBA366 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-Bit Microprocessor |
| IBM25EMPPC740LEBA400 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-Bit Microprocessor |
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