参数资料
型号: IBM25NPE405L-3DA200CZ
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324
封装: 23 MM, PLASTIC, EBGA-324
文件页数: 36/48页
文件大小: 741K
代理商: IBM25NPE405L-3DA200CZ
Advance Information
PowerNPTM NPe405L Embedded Processor Data Sheet
41
I/O Specications—200MHz (Part 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
Ethernet Interface
EMC0MDClk
n/a
7.4
1.5
12
8
1, async
EMC0MDIO
n/a
8.8
1.2
12
8
EMC0MDClk
1
EMC0TxD0:3
[EMC0Tx0:1D0:1
[EMC0Tx0:1D]
n/a
10.5
[7.3]
[5.0]
3.0
[2.3]
[1.7]
12
8
PHYTX
1
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
n/a
11.8
[7.2]
[5.6]
2.9
[2.3]
[1.7]
12
8
PHYTX
1
EMC0TxErr
[EMC0Tx1En]
n/a
11.8[7.4]
2.9[2.4]
12
8
PHYTX
1
PHY0Col[PHY0Rx1Er]l
async[0.2]
async[1.7]
n/a
1
PHY0CrS[PHY0CrS0DV]
async[0.1]
async[1.9]
n/a
1
PHY0RxClk
n/a
1, async
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:1D]
1.5
[0.8]
[0.9]
1.7
[1.7]
[0.3]
n/a
PHYRX
1
PHY0RxDV
[PHY0CRS1DV]
1.3[0.7]
1.7[1.7]
n/a
PHYRX
1
PHY0RxErr[PHY0Rx0Er]
1.3[0.7]
1.8[1.9]
n/a
PHYRX
1
PHY0TxClk[PHY0RefClk]
n/a
1, async
HDLCEX Interface
HDLCEXRxClk
n/a
HDLCEXRxDataA:B
23.8
2.1
n/a
HDLCEXRxFS
24.2
1.1
n/a
HDLCEXTxClk
n/a
HDLCEXTxDataA:B
n/a
10.5
3.3
12
8
HDLCEXTxFS
20.3
1.0
n/a
HDLCEXTxEnA
[GPIO28][UART1_DCD]
n/a
11.3
3.5
12
8
HDLCEXTxEnB
[GPIO29][UART1_RI]
n/a
11.8
3.8
12
8
Internal Peripheral Interface
IICSCL
async
17
11
IICSDA
async
17
11
[UART0_CTS]
async
n/a
[UART0_DCD]
async
n/a
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