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| 型号： | IBM25PPC750CXEJP5513T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件页数： | 36/44页 |
| 文件大小： | 416K |
| 代理商： | IBM25PPC750CXEJP5513T |
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Data Sheet
Preliminary
PowerPC 750CXe RISC Microprocessor
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
System Design Information
Page 33 of 36
6.6.3 Internal Package Conduction Resistance
For the PBGA, described in Table 4-3 on page 8, the primary intrinsic conduction thermal resistance paths
are as follows.
Die junction-to-case thermal resistance
θJC
Die junction-to-lead thermal resistance
θJB
Die junction-to-ambient thermal resistance
θJA
Figure 6-4 depicts the primary heat transfer path for this package.
6.7 Operational and Design Considerations
6.7.1 Level Protection
A level protection feature is included in the PowerPC 750CXe in releases DD2.0 and later. The level
protection feature is available only in the 1.8 V bus mode. This feature prevents ambiguous floating reference
voltages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the I/O voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD; if the I/O level is
closer to GND, the I/O level is pulled low. This self-latching circuitry “keeps” the floating inputs defined and
avoids meta-stability. In Table 6-3, these signals are defined as “Keeper” in the Level Protect column.
Figure 6-4. PBGA Package Thermal Model
External Resistance
Internal Resistance
(Note the internal versus external package resistance.)
Radiation
Convection
Radiation
Convection
Die/Case (
θ
JC)
Printed-Circuit Board
Package/Leads (
θ
JB)
Chip Junction
θ
JA
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相关代理商/技术参数 |
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| IBM25PPC750CXEJP7012T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 600MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP7012T Co-Processors |
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