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参数资料
| 型号： | ICD2053BSC-1 |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 1/9页 |
| 文件大小： | 138K |
| 代理商： | ICD2053BSC-1 |
Programmable Clock Generator
ICD2053B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07134 Rev. **
Revised September 26, 2001
3B
Features
Clock outputs ranging from 391 kHz to 100 MHz (TTL
levels) or 90 MHz (CMOS levels)
2-wire serial interface facilitates programmable output
frequency
Phase-Locked Loop oscillator input derived from exter-
nal reference clock (1 MHz to 25 MHz) or External Crys-
tal (2 MHz to 24 MHz)
Three-State output control disables output for test pur-
poses
Sophisticated internal loop filter requires no external
components or manufacturing tweaks as commonly re-
quired with external filters
Low power consumption makes device ideal for power-
and space-critical applications
8-pin 150-mil packaging achieves minimum footprint
for space-critical applications
5V operation
High-speed CMOS technology
Functional Description
The ICD2053B Programmable Clock Generator offers a fully
user-programmable phase-locked loop in a single 8-pin pack-
age. The output may be changed “on the fly” to any desired
frequency value between 391 kHz and 100 MHz (90 MHz at
CMOS levels). The ICD2053B is ideally suited for any design
in which package size, power, and/or frequency programma-
bility are important design issues.
The ability to dynamically change the output frequency adds a
whole new degree of freedom for the designer. Some exam-
ples of the uses for this device include: laptop computers, in
which slowing the speed of operation can mean less power
consumption; graphics board dot clocks to allow dynamic syn-
chronization of different brands of monitors or display formats;
on-board test strategies where the ability to skew a system’s
desired frequency (e.g.,
±10%) allows worst-case evaluation.
7
5
3
Pin Configuration
2053b-1
1
2
3
4
5
8
7
6
XTALOUT
SCLK
GND
DATA
XTALIN
MUXREF/OE
VDD
CLKOUT
Top View
Logic Block Diagram
XTALOUT
XTALIN
REFERENCE
OSCILLATOR
÷Q
f(REF)
÷2P
f OUT
÷2N
PLL
MUX
CLKOUT
CONTROL LOGIC
SCLK
DATA
MUXREF/OE
VDD
GND
2053b-2
7
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