参数资料
型号: ICS1894K-32LF
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/50页
文件大小: 0K
描述: PHYCEIVER LOW PWR 3.3V 32QFN
标准包装: 490
类型: PHY 收发器
规程: MII,RMII
电源电压: 3.14 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 托盘
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
14
ICS1894-32
REV M 021512
If a crystal is used as the clocking source, connect it to both
the REFIN (pin 30) and REFOUT (pin 29) pins of the
ICS1894-32. A pair of bypass capacitors on either side of
the crystal are connected to ground. The crystal is used in
the parallel resonance or anti-resonance mode. The value
of the load caps serve to adjust the final frequency of the
crystal oscillation. Typical applications would use 25 pF load
caps. The exact value will be affected by the board routing
capacitance on REFIN and REFOUT pins. Smaller load
capacitors raise the frequency of oscillation.
Once the exact value of load capacitance is established it
will be the same for all boards using the same specification
crystal. The best way to measure the crystal frequency is to
measure the frequency of TXCLK (pin 22) using a frequency
counter with a 1 second gate time. Using the buffered output
TXCLK prevents the crystal frequency from being affected
by the measurement. The crystal specification is shown in
the 25MHz Crystal Specification table.
25 MHz Crystal Specification Table
25 MHz Oscillator Specification table
50 MHz Oscillator Specification table
Status Interface
The ICS1894-32 has two multi-function configuration pins
that report the PHY status by providing signals that are
intended for driving LEDs. Configuration is set by Bank0
Register 20.
Specifications
Symbol Minimum
Typical Maximum
Unit
Fundamental Frequency
F0
24.99875 25.00000
25.00125
MHz
Freq. Tolerance
ΔF/f
± 50
ppm
Input Capacitance
Cin
3
pF
Specifications
Symbol Minimum
Typical Maximum
Unit
Output Frequency
F0
24.99875 25.00000
25.00125
MHz
Freq. Stability (including aging)
ΔF/f
± 50
ppm
Duty cycle CMOS level one-half VDD
Tw/T
35
65
%
VIH
2.79
Volts
VIL
0.33
Volts
Specifications
Symbol Minimum
Typical Maximum
Unit
Output Frequency
F0
49.9975 50.00000
50.0025
MHz
Freq. Stability (including aging)
ΔF/f
± 50
ppm
Duty cycle CMOS level one-half VDD
Tw/T
35
65
%
VIH
2.79
Volts
VIL
0.33
Volts
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