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参数资料
| 型号： | ICS541MT |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 1/5页 |
| 文件大小： | 95K |
| 代理商： | ICS541MT |
ICS541
MDS 541 D
1
Revision 073103
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
PLL Clock Divider
EOL - DEVICE NOT RECOMMENDED FOR NEW DESIGNS
Description
The ICS541 is cost effective way to produce a high
quality clock output divided from a clock input. The chip
accepts a clock input up to 135 MHz at 3.3V. Using
proprietary Phase Locked-Loop (PLL) techniques, the
device produces a divide by 1, 2, 4, or 8 of the input
clock. There are two outputs on the chip, one being a
low-skew divide by two of the other.
For instance, if an 80 MHz input clock is used, the
ICS541 can produce low skew 80 MHz and 40 MHz
clocks, or 40 MHz and 20 MHz clocks, or 20 MHz and
10 MHz clocks. The chip has an all-chip power down
mode that stops the outputs low, and an OE pin that
tri-states the outputs.
The ICS541 is a member of ICS’ ClockBlocksTM family
of clock building blocks. See the ICS542 and ICS543
for other clock dividers, and the ICS501, 502, and 503
for clock multipliers.
Features
8 pin SOIC package
Low cost clock divider and 2X multiplier
Low skew (500 ps) outputs. One is /2 of the other
East to use with other generators and buffers
Input clock frequency up to 135 MHz at 3.3 V
Input clock frequency up to 156 MHz at 5V
Tolerant of poor input clock duty cycle, jitter
Output clock duty cycle of 45/55
Power Down turns off chip
Output Enable
Full CMOS clock swings with 25 mA drive capability
at TTL levels
Advanced, low power CMOS process
Operating voltage of 3.3V or 5V
Device not recommended for new designs.
Please see the ICS527-01 as a replacement.
Block Diagram
Input Clock
Divider
and
Selection
Circuitry
CLK1
CLK2
S1, S0
/2
OE (both outputs)
GND
VDD
相关PDF资料 |
PDF描述 |
|---|---|
| ICS544MI-01 | 156 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS544M-01LF | 156 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS544MI-01T | 156 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS554-01DPK | 156 MHz, OTHER CLOCK GENERATOR, UUC |
| ICS548G-05LFT | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS542 | 制造商:ICS 制造商全称:ICS 功能描述:Clock Divider |
| ICS542-DPK | 制造商:Integrated Device Technology Inc 功能描述:IC DIVIDER USER CONFIG 8-SOIC |
| ICS542M | 功能描述:IC CLOCK BUFF DIVIDER 1:2 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
| ICS542MI | 功能描述:IC CLOCK BUFF DIVIDER 1:2 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
| ICS542MILF | 功能描述:IC CLOCK BUFF DIVIDER 1:2 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 产品培训模块:High Bandwidth Product Overview 标准包装:1,000 系列:Precision Edge® 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:4 差分 - 输入:输出:是/是 输入:CML，LVDS，LVPECL 输出:CML 频率 - 最大:2.5GHz 电源电压:2.375 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) |
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