参数资料
型号: ICS541MT
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 3/5页
文件大小: 95K
代理商: ICS541MT
PLL Clock Divider
MDS 541 D
3
Revision 073103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800
www.icst.com
ICS541
bead and bulk decoupling from the device is less
critical.
2) To minimize EMI the 33
W series termination resistor,
if needed, should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS541. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS541. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
°C
Storage Temperature
-65 to +150
°C
Junction Temperature
175
°C
Soldering Temperature
260
°C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
°C
Power Supply Voltage (measured in respect to GND)
3.0
5.5
V
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