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参数资料
| 型号： | ICS541MT |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 2/5页 |
| 文件大小： | 95K |
| 代理商： | ICS541MT |
PLL Clock Divider
MDS 541 D
2
Revision 073103
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
ICS541
Pin Assignment
8 pin (150 mil) SOIC
Clock Decoding Table
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
W trace (a
commonly used trace impedance), place a 33
W resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
W.
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS541 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
ICLK
VDD
GND
CLK/ 2
S0
OE
S1
CLK
1
2
3
4
8
7
6
5
S1
#5
S0
#4
CLK
pin 8
CLK
pin 7
0
Power Down All
0
1
Input/4
Input/8
1
0
Input
Input/2
1
Input/2
Input/4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
XI
Clock input.
2
VDD
Power
Connect to +3.3V or +5V.
3
GND
Power
Connect to ground.
4
S0
Input
Select 0 for output clock. Connect to GND or VDD, per decoding table above.
5
S1
Input
Select 1 for output clock. Connect to GND or VDD, per decoding table above.
6
OE
Input
Output Enable. Tri-states both output clocks when low.
7
CLK/2
Output
Clock output per table above. Low skew divide by two of pin 8 clock.
8
CLK
Output
Clock output per table above.
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