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参数资料
| 型号： | ICS663MT |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 2/7页 |
| 文件大小： | 146K |
| 代理商： | ICS663MT |
PLL BUILDING BLOCK
MDS 663 D
2
Revision 062904
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
ICS663
Pin Assignment
VCO Post Divide Select Table
0 = connect pin directly to ground
1 = connect pin directly to VDD
Pin Descriptions
1
2
3
FBIN
4
VDD
GND
CLK
LF
SEL
LFR
8
7
6
5
REFIN
8 Pin (150 mil) SOIC
SEL
VCO Post
Divide
08
12
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
FBIN
Input
Feedback clock input. Connect the output of the feedback divider to
this pin. Falling edge triggered.
2
VDD
Power
VDD. Connect to +3.3 V or +5 V.
3
GND
Power
Connect to ground.
4
LF
Input
Loop filter connection (refer to Figure 1 on Page 5).
When using the phase detector block only, this pin serves as the
charge pump output.
When using the VCO block only, this pin serves as VCO input control
voltage.
5
LFR
Input
Loop filter return (refer to Figure 1 on Page 5).
6
SEL
Input
Select pin for VCO post divide, as per above table.
7
CLK
Output
Clock output.
8
REFIN
Input
Reference clock input. Connect the input clock to this pin. Falling edge
triggered.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS663M | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS664G-03LFT | 148.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664G-03T | 148.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664G-03 | 148.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS664G-04TR | 148.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS664-01 | 制造商:ICS 制造商全称:ICS 功能描述:Digital Video Clock Source |
| ICS664-02 | 制造商:ICS 制造商全称:ICS 功能描述:PECL Digital Video Clock Source |
| ICS664-03 | 制造商:ICS 制造商全称:ICS 功能描述:Digital Video Clock Source |
| ICS664-03LF | 制造商:ICS 制造商全称:ICS 功能描述:Digital Video Clock Source |
| ICS664-03LFT | 制造商:ICS 制造商全称:ICS 功能描述:Digital Video Clock Source |
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