参数资料
型号: ICS8745BYIT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件页数: 4/20页
文件大小: 1383K
代理商: ICS8745BYIT
ICS8745BI
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
12
ICS8745BYIREV. C APRIL 16, 2007
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
CLK/CLK INPUT:
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1k
resistor can be tied from CLK to
ground.
Outputs:
LVDS Output
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, we
recommend that there is no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100
differential transmission line environment, LVDS drivers require a
matched load termination of 100
across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100
+
3.3V
50
50
100
Differential Transmission Line
相关PDF资料
PDF描述
ICS8745BYI 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS874S02AMILF 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02AMI 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02AMIT 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02BMILF 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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