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参数资料
| 型号： | ICS9248YF-199-T |
| 英文描述： | Frequency Generator for SIS 735/740 with AMD K7 Processor |
| 中文描述： | 频率发生器与AMD k7的处理器为SIS的740分之735 |
| 文件页数： | 3/21页 |
| 文件大小： | 181K |
| 代理商： | ICS9248YF-199-T |
3
ICS9248-199
0376E—12/23/02
General Description
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDD48 = 48MHz, 24MHz, fixed PLL
VDDA = Core, PLL, X1, X2
VDDAGP=AGP, REF
The
ICS9248-199
is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133
or DDR memory. It provides all necessary clock signals for such a system.
The
ICS9248-199
is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub).
This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing
the use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency
setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and
enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to
0.1MHz increment.
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK
SDRAM
PCICLK (4:0)
AGPCLK (1:0)
IOAPIC
PCICLK_F
2
5
2
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
AGP_STOP#
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
AGP
DIVDER
Stop
IOAPIC
DIVDER
CPUCLKT0
CPUCLKC0
Block Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-39 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-64 | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7TM System Clock Chip |
| ICS9248YF-65 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENDIUM II Systems |
| ICS9248YF-66 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-72 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
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